Patents by Inventor Sadayuki Ohnishi

Sadayuki Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040041269
    Abstract: An SiCN layer 108, BCB layer 110 and MSQ layer 112 are deposited in this sequence on a copper interconnect line constituted by a barrier metal layer 104 and a copper layer 106. The BCB layer 110 is formed by plasma polymerization of a monomer containing a divinylsiloxane bisbenzocyclobutene unit.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 4, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Sadayuki Ohnishi
  • Publication number: 20030155657
    Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 21, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takashi Tonegawa, Koji Arita, Tatsuya Usami, Noboru Morita, Koichi Ohto, Yoichi Sasaki, Sadayuki Ohnishi, Ryohei Kitao
  • Patent number: 5691220
    Abstract: A stacked storage capacitor of a dynamic random access memory cell has a p-type polysilicon layer forming an upper part of an accumulating electrode, a dielectric film structure and a p-type polysilicon counter electrode, and boron difluoride is ion implanted into a non-doped polysilicon layer for the counter electrode so as to decrease leakage current density rather than a boron-implanted polysilicon counter electrode.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: November 25, 1997
    Assignee: NEC Corporation
    Inventors: Sadayuki Ohnishi, Koichi Ando
  • Patent number: 5397748
    Abstract: A thermal oxidation method for producing a semiconductor device having a capacitor insulating film structure capable of making a thin film having a small leakage current and small temperature dependence of the leakage current. In the insulating film, a silicon nitride film with a small electron mobility and a silicon oxide film with a small hole mobility are alternately laminated in order of the nitride film/oxide film/nitride film/oxide film from a lower electrode side. A current component such as electrons flowing in this insulating film structure is limited by the layer with the smaller mobility to reduce the leakage current. An oxide film thickness of approximately several .ANG. can thus be strictly controlled. By forming the silicon nitride film between the high dielectric oxide film and the electrode, the reaction of the silicon electrode and the high dielectric oxide film can be prevented.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: March 14, 1995
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Sadayuki Ohnishi