Patents by Inventor Sadayuki Okuma

Sadayuki Okuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080258315
    Abstract: The present invention aims to provide a semiconductor device which can enhance area efficiency, and the semiconductor device includes a plurality of electroconductive member regions formed in a predetermined layer, an insulating film region which is formed in the insulating layer which is an upper layer of the predetermined layer and which covers a region other than at least the plurality of electroconductive member regions, and wiring for making a connection which is formed along the insulating film region and which connects the plurality of electroconductive member regions mutually.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 23, 2008
    Applicant: ELPIDA MEMORY , INC.
    Inventor: Sadayuki Okuma
  • Publication number: 20080225620
    Abstract: In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Atsushi Masumizu, Sadayuki Okuma
  • Publication number: 20060220263
    Abstract: A plurality of first pads for bonding is arranged in a central portion of a semiconductor device in a longitudinal direction of the device. In an edge portion of the semiconductor device, a plurality of second pads for bonding is arranged in the longitudinal direction of the device. The first pad and the second pad are connected by a wiring.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Inventors: Toshihiro Waki, Sadayuki Okuma
  • Patent number: 6975026
    Abstract: A package for mounting a semiconductor device has a surface exposed to an atmosphere. The exposed surface is covered with a covering material such as a paint, a tape or a seal.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: December 13, 2005
    Assignees: Elpida Memory, Inc., Renesas Eastern Japan Semiconductor, Inc., Hitachi, Ltd.
    Inventors: Morihiko Mouri, Sadayuki Okuma, Yasushi Takahashi, Takao Ono, Yosihiro Sakaguchi, Atsushi Nakamura, Toshio Miyazawa
  • Publication number: 20050229135
    Abstract: It is an object of the present invention to realize a circuit diagram creating method and circuit diagram creating apparatus capable of efficiently acquiring information on a lower layer, and a circuit diagram creating method for creating a layered electric circuit diagram from data indicating an electric circuit that includes the steps of determining an outline area to be displayed from wiring information and graphics information which are data indicating the electric circuit for symbol graphics of a lower layer and displaying information on the circuit diagram so as not to go beyond the outline area.
    Type: Application
    Filed: March 23, 2005
    Publication date: October 13, 2005
    Inventor: Sadayuki Okuma
  • Publication number: 20040007383
    Abstract: A package for mounting a semiconductor device has a surface exposed to an atmosphere. The exposed surface is covered with a covering material such as a paint, a tape or a seal.
    Type: Application
    Filed: April 10, 2003
    Publication date: January 15, 2004
    Inventors: Morihiko Mouri, Sadayuki Okuma, Yasushi Takahashi, Takao Ono, Yosihiro Sakaguchi, Atsushi Nakamura, Toshio Miyazawa
  • Patent number: 6496403
    Abstract: Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: December 17, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Sadayuki Okuma, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi
  • Publication number: 20020012285
    Abstract: Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.
    Type: Application
    Filed: July 18, 2001
    Publication date: January 31, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Sadayuki Okuma, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi