Abstract: Systems and methods can suggest applications and/or recipients for a user of a computing device to perform communication. The suggestions can be provided on a user interface for a user to select. A suggestion engine can use historical user interactions that include a recipient, a communication application used to communicate with the recipient, and contextual data to determine which application and/or recipients to suggest. The user interactions may occur in a variety of ways, e.g., after a content object has been selected within a host application, where a communication application is selected thereafter. Multiple models may be used to provide the suggestions, such as a pattern model or a cluster model that uses recent user interactions. As another example, a heuristics model may also be used.

Abstract: Systems and methods can suggest applications and/or recipients for a user of a computing device to perform communication. The suggestions can be provided on a user interface for a user to select. A suggestion engine can use historical user interactions that include a recipient, a communication application used to communicate with the recipient, and contextual data to determine which application and/or recipients to suggest. The user interactions may occur in a variety of ways, e.g., after a content object has been selected within a host application, where a communication application is selected thereafter. Multiple models may be used to provide the suggestions, such as a pattern model or a cluster model that uses recent user interactions. As another example, a heuristics model may also be used.

Abstract: One embodiment provides a system comprising at least one learner application module for receiving feedback data from at least one user via at least one electronic device, about information presented to the users by a presenter. The system further comprises at least one sensor for capturing contextual data associated with the users. The system further comprises a recommendation provider for collecting feedback data and contextual data from each learner application module and each sensor, respectively. The recommendation provider determines at least one personalized recommendation for each user based on the collected data and the presented information.

Abstract: In some embodiments, computer implemented methods, systems, and computer readable media can receive a notification from at least one of a plurality of notification nodes. The notification can be associated with a target user. Information related to the target user can be acquired. Information related to the plurality of notification nodes can be acquired. The plurality of notification nodes can be ranked based on at least one of the information related to the target user or the information related to the plurality of notification nodes. Then one or more notification nodes that satisfy one or more specified ranking criteria can be selected. The notification can be formatted based on at least one of the information related to the target user or information related to the one or more selected notification nodes. The formatted notification can then be transmitted to the one or more selected notification nodes.

Abstract: A crystal oscillator achieves fast start-up by injecting an in-band periodic signal into the crystal oscillator driver circuit. The in-band periodic signal has a frequency that is within a bandwidth of the crystal oscillator. Injection of the in-band periodic signal begins in response to a power-up condition and stops after a predetermined time period corresponding to the amount of time it takes to ensure the crystal driver is achieving full swing.

Abstract: One embodiment provides a system comprising at least one learner application module for receiving feedback data from at least one user via at least one electronic device, about information presented to the users by a presenter. The system further comprises at least one sensor for capturing contextual data associated with the users. The system further comprises a recommendation provider for collecting feedback data and contextual data from each learner application module and each sensor, respectively. The recommendation provider determines at least one personalized recommendation for each user based on the collected data and the presented information.

Abstract: In some embodiments, computer implemented methods, systems, and computer readable media can receive a notification from at least one of a plurality of notification nodes. The notification can be associated with a target user. Information related to the target user can be acquired. Information related to the plurality of notification nodes can be acquired. The plurality of notification nodes can be ranked based on at least one of the information related to the target user or the information related to the plurality of notification nodes. Then one or more notification nodes that satisfy one or more specified ranking criteria can be selected. The notification can be formatted based on at least one of the information related to the target user or information related to the one or more selected notification nodes. The formatted notification can then be transmitted to the one or more selected notification nodes.

Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Abstract: The loop bandwidth of a PLL is adjusted based on a difference between the output signal of the PLL and the PLL reference signal. In an embodiment, the DC open loop gain and natural frequency of the PLL are adjusted based on the phase difference between the output signal and the reference signal, so that the loop bandwidth of the PLL is increased when the phase difference is outside a programmable range and is decreased when the phase difference is within the programmable range.

Abstract: Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.

Abstract: An amplifier circuit includes a first stage and a second stage. The first stage includes a differential input circuit coupled to a differential input node. The first stage includes a first partial cascode circuit including devices of a first type, the first partial cascode circuit being coupled to a first power supply node, a first bias node, and the differential input stage. The first stage includes a second partial cascode circuit including devices of a second type, the second partial cascode circuit being coupled to a second power supply node and the differential input circuit. The second stage is coupled to the first stage. The second stage includes a first full cascode circuit coupled to an output node.

Abstract: An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.

Abstract: An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.

Abstract: An amplifier circuit includes a first stage and a second stage. The first stage includes a differential input circuit coupled to a differential input node. The first stage includes a first partial cascode circuit including devices of a first type, the first partial cascode circuit being coupled to a first power supply node, a first bias node, and the differential input stage. The first stage includes a second partial cascode circuit including devices of a second type, the second partial cascode circuit being coupled to a second power supply node and the differential input circuit. The second stage is coupled to the first stage. The second stage includes a first full cascode circuit coupled to an output node.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: An apparatus includes a filter module, an amplification module, and an adjustment signal source. The filter module generates a filtered signal based on a received signal. This filtered signal has a level shift corresponding to a difference between a direct current (DC) level of the filtered signal and a DC level of the received signal. From the filtered signal and an adjustment signal, the amplification module generates an amplified signal. The adjustment signal, which is provided by the adjustment signal source, may control (e.g., diminish) an effect of the level shift on a DC level of the amplified signal.

Abstract: An apparatus includes a filter module, an amplification module, and an adjustment signal source. The filter module generates a filtered signal based on a received signal. This filtered signal has a level shift corresponding to a difference between a direct current (DC) level of the filtered signal and a DC level of the received signal. From the filtered signal and an adjustment signal, the amplification module generates an amplified signal. The adjustment signal, which is provided by the adjustment signal source, may control (e.g., diminish) an effect of the level shift on a DC level of the amplified signal.

Abstract: Various embodiments for a partial cascode delay locked loop architecture are described. In one embodiment, an apparatus may include a delay locked loop circuit having a plurality of partial cascode circuits. The plurality of partial cascode circuits may be arranged to reduce phase noise from a ground power supply voltage and a power supply voltage. Other embodiments are described and claimed.