Abstract: Various embodiments for a partial cascode phase locked loop architecture are described. In one embodiment, an apparatus may include a phase locked loop circuit having a plurality of partial cascode circuits. The plurality of partial cascode circuits may be arranged to reduce phase noise from a ground power supply voltage and a power supply voltage. Other embodiments are described and claimed.

Abstract: Apparatus, system, and method including a single common node bias voltage; at least a first current path to drive a bias current based on the single common node bias voltage; at least a first current mirror to mirror the bias current in a second current path; and an output current path comprising current drivers to drive source and sink currents that are matched to the bias current. The first current mirror may include at least one partial cascode current mirror. The apparatus and system provide a single common node bias voltage to generate a bias current; mirror the bias current in at least one current path; and output well-matched output source and sink currents based on the bias current.

Abstract: A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (KVCDL). Low KVCDL values leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Abstract: A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the delayed output signal and producing an error signal. Each of the delay elements includes a first input associated with a negative output and a second input associated with a positive output, whereby the positive and negative outputs are selectively coupled to a constant voltage source responsive to a first bias voltage and to a ground. The positive and negative outputs are responsive to a second bias voltage and the first and second voltage inputs. The constant voltage source and the positive output are coupled via a first transistor and the constant voltage source and negative output are coupled via being a second transistor.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

Abstract: A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to control a plurality of differential delay elements. The bias generator includes a bias current generator having a fixed voltage-controlled current source and a dynamic voltage-controlled current source to generate a bias current, and a bias voltage generator for receiving the bias current and generating first and second bias voltages. The bias generator can generate multiple current levels in different modes of operation. Each of the current levels of the bias generator allows a small range of currents and therefore small values of gain factors (KVCDL). Low KVCDL values leads to lower jitter and better control over feedback stability, resulting in an increase in the range of operational frequencies.

Abstract: A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference between the input signal and the output signal is zero, and a delay element control circuit for increasing and decreasing the phase of the output signal. This circuit design reduces processing delay, improves jitter performance, and extends the DLL operating frequency range.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.

Abstract: A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference between the input signal and the output signal is zero, and a delay element control circuit for increasing and decreasing the phase of the output signal. This circuit design reduces processing delay, improves jitter performance, and extends the DLL operating frequency range.