Abstract: A speech recognition system utilizes multiple quantizers to process frequency parameters and mean compensated frequency parameters derived from an input signal. The quantizers may be matrix and vector quantizer pairs, and such quantizer pairs may also function as front ends to a second stage speech classifiers such as hidden Markov models (HMMs) and/or utilizes neural network postprocessing to, for example, improve speech recognition performance. Mean compensating the frequency parameters can remove noise frequency components that remain approximately constant during the duration of the input signal. HMM initial state and state transition probabilities derived from common quantizer types and the same input signal may be consolidated to improve recognition system performance and efficiency. Matrix quantization exploits the “evolution” of the speech short-term spectral envelopes as well as frequency domain information, and vector quantization (VQ) primarily operates on frequency domain information.

Abstract: A speech recognition system utilizes both matrix and vector quantizers as front ends to a second stage speech classifier such as hidden Markov models (HMMs) and utilizes neural network postprocessing to, for example, improve speech recognition performance. Matrix quantization exploits the “evolution” of the speech short-term spectral envelopes as well as frequency domain information, and vector quantization (VQ) primarily operates on frequency domain information. Time domain information may be substantially limited which may introduce error into the matrix quantization, and the VQ may provide error compensation. The matrix and vector quantizers may split spectral subbands to target selected frequencies for enhanced processing and may use fuzzy associations to develop fuzzy observation sequence data. A mixer provides a variety of input data to the neural network for classification determination. The neural network's ability to analyze the input data generally enhances recognition accuracy.

Abstract: The communications processor of the present invention comprises, in a single integrated circuit chip, the combination of a central processing unit (CPU) having an execution unit with an arithmetic logic unit and accumulators, a program counter, memory, a clock generator, a timer, a bus interface, chip select outputs, and an interrupt processor; a digital signal processor (DSP) having an instruction set to carry out a digital signal processing algorithm, an execution unit for carrying out multiply and accumulate operations and an external interface; an address bus connected between the CPU and the DSP; a data bus connected between the CPU and the DSP; and a static scheduler for statically scheduling execution of the signal processing algorithm between the digital signal processor and the CPU.

Abstract: A speech recognition system utilizes multiple quantizers to process frequency parameters and mean compensated frequency parameters derived from an input signal. The quantizers may be matrix and vector quantizer pairs, and such quantizer pairs may also function as front ends to a second stage speech classifiers such as hidden Markov models (HMMs) and/or utilizes neural network postprocessing to, for example, improve speech recognition performance. Mean compensating the frequency parameters can remove noise frequency components that remain approximately constant during the duration of the input signal. HMM initial state and state transition probabilities derived from common quantizer types and the same input signal may be consolidated to improve recognition system performance and efficiency. Matrix quantization exploits the “evolution” of the speech short-term spectral envelopes as well as frequency domain information, and vector quantization (VQ) primarily operates on frequency domain information.

Abstract: A method of communicating via an electronic mail system includes creating a text portion of a message. An audio portion of the message is also recorded. The audio portion is digitized. The digitized audio portion is coupled to the text portion to form a complete message. The complete message is transmitted via the electronic mail system. The complete message is received at a destination unit, which provides for the visual displaying of the text portion of the message, together with the audio outputting of the audio portion of the message.

Abstract: A speech recognition system utilizes both matrix and vector quantizers as front ends to a second stage speech classifier. Matrix quantization exploits input signal information in both frequency and time domains, and the vector quantizer primarily operates on frequency domain information. However, in some circumstances, time domain information may be substantially limited which may introduce error into the matrix quantization. Information derived from vector quantization may be utilized by a hybrid decision generator to error compensate information derived from matrix quantization. Additionally, fuzz methods of quantization and robust distance measures may be introduced to also enhance speech recognition accuracy. Furthermore, other speech classification stages may be used, such as hidden Markov models which introduce probabilistic processes to further enhance speech recognition accuracy.

Abstract: A speech recognition system utilizes both split matrix and split vector quantizers as front ends to a second stage speech classifier such as hidden Markov models (HMMs) to, for example, efficiently utilize processing resources and improve speech recognition performance. Fuzzy split matrix quantization (FSMQ) exploits the "evolution" of the speech short-term spectral envelopes as well as frequency domain information, and fuzzy split vector quantization (FSVQ) primarily operates on frequency domain information. Time domain information may be substantially limited which may introduce error into the matrix quantization, and the FSVQ may provide error compensation. Additionally, acoustic noise influence may affect particular frequency domain subbands. This system also, for example, exploits the localized noise by efficiently allocating enhanced processing technology to target noise-affected input signal parameters and minimize noise influence.

Abstract: One embodiment of a speech recognition system is organized with speech input signal preprocessing and feature extraction followed by a fuzzy matrix quantizer (FMQ) designed with respective codebook sets at multiple signal to noise ratios. The FMQ quantizes various training words from a set of vocabulary words and produces observation sequences O output data to train a hidden Markov model (HMM) processes .lambda.j and produces fuzzy distance measure output data for each vocabulary word codebook. A fuzzy Viterbi algorithm is used by a processor to compute maximum likelihood probabilities PR(O.vertline..lambda.j) for each vocabulary word. The fuzzy distance measures and maximum likelihood probabilities are mixed in a variety of ways to preferably optimize speech recognition accuracy and speech recognition speed performance.

Abstract: One embodiment of a speech recognition system is organized with speech input signal preprocessing and feature extraction followed by a fuzzy matrix quantizer (FMQ). Frames of the speech input signal are represented by a vector .function. of line spectral pair frequencies and are fuzzy matrix quantized to respective a vector .function. entries in a codebook of the FMQ. A distance measure between .function. and .function., d(.function.,.function.), is defined as ##EQU1## where the constants .alpha..sub.1, a.sub.2, .beta..sub.1 and .beta..sub.2 are set to substantially minimize quantization error, and e.sub.i is the error power spectrum of the speech input signal and a predicted speech input signal at the ith line spectral pair frequency of the speech input signal. The speech recognition system may also include hidden Markov models and neural networks, such as a multilevel perceptron neural network, speech classifiers.

Abstract: One embodiment of a speech recognition system is organized with speech input signal preprocessing and feature extraction followed by a fuzzy matrix quantizer (FMQ). Frames of the speech input signal are represented in a matrix by a vectorf of line spectral pair frequencies and energy coefficients and are fuzzy matrix quantized to respective vector f entries of a matrix codeword in a codebook of the FMQ. The energy coefficients include the original energy and the first and second derivatives of the original energy which increase recognition accuracy by, for example, being generally distinctive speech input signal parameters and providing noise signal suppression especially when the noise signal has a relatively constant energy over at least two time frame intervals. To reduce data while maintaining sufficient resolution, the energy coefficients may be normalized and logarithmically represented. A distance measure between f and f, d(f, f), is defined as ##EQU1## where the constants .alpha..sub.1, .alpha..sub.

Abstract: In one embodiment, a speech recognition system is organized with a fuzzy matrix quantizer with a single codebook representing u codewords. The single codebook is designed with entries from u codebooks which are designed with respective words at multiple signal to noise ratio levels. Such entries are, in one embodiment, centroids of clustered training data. The training data is, in one embodiment, derived from line spectral frequency pairs representing respective speech input signals at various signal to noise ratios. The single codebook trained in this manner provides a codebook for a robust front end speech processor, such as the fuzzy matrix quantizer, for training a speech classifier such as a u hidden Markov models and a speech post classifier such as a neural network. In one embodiment, a fuzzy Viterbi algorithm is used with the hidden Markov models to describe the speech input signal probabilistically.

Abstract: A storage device stores data on a disk. A storage device can be a electromagnetic or optical storage device. The storage device utilizes a motion control circuit having a digital signal processor and central processing unit integrated on a single substrate. The central processing unit and digital signal processor cooperate to affect motion control operations for the storage device. The motion control circuit partitions complex and non-complex mathematical instructions between the digital signal processor and the general purpose central processing unit.

Abstract: An apparatus for processing signals including a signal receiving circuit, a first processing circuit executing a first set of instructions, a second processing circuit executing a second set of instructions implementing a digital signal processing algorithm, an output circuit for outputting processed signals, and a communication circuit for communicatingly connecting the signal receiving circuit, the first processing circuit, the second processing circuit, and the output circuit. The first set of instructions includes control instructions for controlling operation of the apparatus and first operational instructions for processing signals; the second set of instructions includes second operational instructions for processing signals; selected of the second operational instructions produce interrupt results. When the first processing circuit receives an interrupt result it processes the interrupt result as a priority interrupt in executing the first set of instructions.

Abstract: An apparatus and method for locating a plurality of roots of a line spectrum pair expression on a unit circle.

Abstract: An apparatus and method for synthesizing a sinusoidal signal generated from a plurality of sample values taken at sample times in succeeding sample intervals. The signal is defined by a parameter which varies by a step value during predetermined sample intervals when the parameter changes from a first value to a second value. The apparatus includes a first logic unit for iteratively treating an initial step value to generate succeeding samples of the step value and a next step value. The next step value is the step value in a next-succeeding sample interval. A second logic unit is included for iteratively generating a next parameter value which is the parameter value during the next-succeeding sample interval. The second logic unit receives succeeding samples of the step value and iteratively generates succeeding samples of an interim parameter value and succeeding samples of a derivative interim parameter value.

Abstract: An apparatus and method are provided for discriminating noise in a received signal. The apparatus comprises a first signal processing means, a second signal processing means, a threshold generating means for generating a threshold value. The first signal processing means generates iteration signal samples and predicted iteration signal samples, compares the iteration signal samples and predicted signal samples to generate a predicted error parameter. The second signal processing means generates a threshold adjustment value based on generated successive iteration signal samples. A logic means logically treats the prediction error parameter, the threshold adjustment value and the threshold value to generate a noise indication value.

Abstract: An apparatus and method for discriminating and suppressing noise within an incoming signal including a first signal processor to generate a first signal representing the incoming signal; a second signal processor to generate a second signal representing the first signal; a prediction device which generates a prediction for the second signal; a logic device which determines the difference between the second signal and the prediction and generates a logic output having a first value when the difference exceeds a threshold and a second value when the difference does not exceed the threshold; and a muting device to mute the incoming signal when the logic output has one value and not mute the incoming signal when the logic output has the other value.

Abstract: A method and apparatus for determining the product of a plurality of N numbers are disclosed. The preferred embodiment of the method includes the steps of: (1) determining a plurality of partial products made up of respective partial products for each combination of the digits of each of the N numbers, each partial product having a combinational significance established by the significance of each digit involved in the respective partial product; (2) providing a register having a plurality of register cells, each having a hierarchical significance; (3) accumulating selected of the partial products to produce accumulated values in specified of the register cells according to the following relationships: P[m,n,o,p, . . . ].fwdarw.[accumulates in].fwdarw.r[x]; x=(m+n+o+p+ . . . )-(N-1), where P[m,n,o,p, . . . ] represents the partial product; "m" represents the first digit's significance (m=1, 2, . . . ); "n" represents the second digit's significance (n=1, 2, . . . ); "o", "p", and " . . .

Abstract: A method and apparatus are disclosed for determining the product of N numbers in base Z. The method includes the steps of: (1) providing a first and succeeding storage arrays. The first storage array includes storage loci containing indicia of products of a first digit and a second digit. A first pointer is positioned by the first digit, a second pointer is positioned by the second digit, and the pointers cooperate to identify a first solution locus containing a first product. Succeeding storage arrays are associated with succeeding N numbers. The first and second pointers identify a subset of storage loci in a succeeding storage array. A third pointer associated with a third digit identifies a second solution locus among the subset. Each array's pointers cooperate to designate a next-succeeding array and a subset of storage loci, and each next-succeeding array has a pointer associated with a next digit to designate a next solution locus until N numbers are involved in the product.

Abstract: A digital signal processing apparatus which employs a ROM-stored library of predetermined instructions which are user-accessible via a sequencer for execution as a program of instructions. The apparatus preferably may also include an instruction RAM which is user-programmable to supplement the prestored instructions in the on-board instruction ROM.