Abstract: An apparatus and method for discriminating and suppressing noise within an incoming signal which provide a first signal processing unit for processing the incoming signal to generate a first iteration signal representing average difference signal level of the incoming signal; a second signal processing unit for processing the first iteration signal to generate a second iteration signal representing specified aspects of the first iteration signal; a prediction unit for generating a predicted value for the second iteration signal from earlier samples of the second iteration signal; a logic unit for determining a threshold difference between the second iteration signal and the predicted value, the logic unit generating a logic output having a first value when the threshold difference exceeds a predetermined threshold value and having a second value when the threshold difference does not exceed the predetermined threshold value; and a muting unit for muting signals which is operatively connected to receive the in

Abstract: An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.

Abstract: An apparatus for adaptively tuning to a received periodic signal. The apparatus preferably employs digital signal processing techniques for algorithmic generation of a sinusoidal estimated output signal, determines the difference between the estimated output signal and the received signal, and generates an error signal based upon the difference between the estimated output signal and the received signal. The error signal is applied to vary at least one factor of the algorithmic determination of the estimated output signal appropriately to reduce the error between the estimated output signal and the received signal.

Abstract: An apparatus for adaptively tuning to a received periodic signal. The apparatus preferably employs digital signal processing techniques for algorithmic generation of a sinusoidal estimated output signal, determines the difference between the estimated output signal and the received signal, and generates an error signal based upon the difference between the estimated output signal and the received signal. The error signal is applied to vary at least one factor of the algorithmic determination of the estimated output signal appropriately to reduce the error between the estimated output signal and the received signal.

Abstract: A method and apparatus provide a noise detector generating a logic output indicating presence of noise in an incoming signal and an attenuation controller for providing a stepped-response to noise operatively connected to respond to the logic output to record a count of noise detections.

Abstract: A method and apparatus for determining the product of a plurality of numbers are disclosed. The preferred embodiment of the method includes the steps of: (1) determining a plurality of respective partial products for each pair-combination of a first number's digits and a second number's digits; (2) providing a register having a plurality of register cells, each having a hierarchical significance; (3) accumulating selected of the respective partial products to produce accumulated values in specified of the register cells according to the following relationships: P.sub.m,n --[accumulates in].fwdarw.r.sub.x ; x=(m+n)-1, where "P.sub.m,n " represents the respective partial product; "m" represents the first number's significance (m=1, 2, . . . ); "n" represents the second number's significance (n=1, 2, . . . ); and "r.sub.

Abstract: An apparatus is disclosed for generating an output signal in response to an input signal having a variable input level. The output signal has an output frequency which varies to represent variations in the input level. The apparatus comprises a processing circuit for implementing a digital signal processing algorithm to generate control signals in response to the input signal, which control signals are representative of the variable input level, and an oscillator circuit for generating the output signal in response to the control signals. The control signals include a first control signal representing a first output frequency, a second control signal representing a second output frequency, and at least one intermediate control signal representing output frequencies intermediate the first and second output frequencies.

Abstract: An apparatus for controlling power delivery from a power source to selected portions of a multiplying device for determining the product of a first number having a first plurality of digits and a second number having a second plurality of digits. The multiplying device includes a plurality of components which include a plurality of multiplier units for determining a plurality of partial products and a register unit for storing information, the register unit including plurality of register cells for accumulatingly storing the partial products according to a predetermined arrangement; the apparatus includes: a power bus for providing controllable delivery paths for delivering the power from the power source to the multiplying device; and a control unit for controlling the delivery paths to selectively effect operational connection between specified components and the power source.

Abstract: An apparatus is disclosed for generating an output signal in response to an input signal having a variable input level. The output signal has an output frequency which varies to represent variations in the input level. The apparatus comprises a processing circuit for implementing a digital signal processing algorithm to generate control signals in response to the input signal, which control signals are representative of the variable input level, and an oscillator circuit for generating the output signal in response to the control signals. The control signals include a first control signal representing a first output frequency, a second control signal representing a second output frequency, and at least one intermediate control signal representing output frequencies intermediate the first and second output frequencies.

Abstract: A method and apparatus for determining the product of a first number and a second number are disclosed. The preferred embodiment of the method includes the steps of: (1) determining a plurality of respective partial products for each pair-combination of the first number's digits and the second number's digits; (2) providing a register having a plurality of register cells, each having a hierarchical significance; (3) accumulating selected of the respective partial products to produce accumulated values in specified of the register cells according to the following relationships: P.sub.m,n --[accumulates in].fwdarw.r.sub.x ; x=(m+n)-1, where "P.sub.m,n " represents the respective partial product; "m" represents the first number's significance (m=1, 2, . . . ); "n" represents the second number's significance (n=1,2, . . . ); and "r.sub.

Abstract: An apparatus adaptable for use with a digital-analog conversion device for effecting communications from a digital device to an analog device, having a digital-analog circuit for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the digital-analog device. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of interpolation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of interpolation.

Abstract: An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of outgoing digital signals to outgoing analog signals.

Abstract: An apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device, the analog-digital conversion device converting incoming analog signals received from the analog device to incoming digital signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation.

Abstract: An apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device, the analog-digital-analog conversion device converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation.

Abstract: Apparatus is provided for performing a method for detecting and correcting errors in one clock cycle that occur during arithmetic operations of at least two operands. Specifically, two operands are operated on to obtain a result. The digits of the result are added to one another. This adding step is repeated until a first single digit is achieved. The digits of each of the operands are added to one another to obtain an intermediate sum. The digits of the intermediate sum, in turn, are added to one another. Once again, this operation is repeated until a second single digit is achieved. The first single digit number is compared with the second single digit number and a signal indicative of error is generated if the comparison is unsuccessful.In order to correct the error, the digits of each of the operands are added to one another to obtain an intermediate sum. Sequentially, a digit is subtracted from the partial sum of the remaining digits of each of the operands.

Abstract: An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of interpolated outgoing digital signals to outgoing analog signals.

Abstract: Method and apparatus for processing digital signals represented as binary words, employing a portion of each word (a "slice") to afford appropriate accuracy. Particularly suited to medium- to high-speed telecommunications applications. In an exemplary transversal filtering operating application, only the high-order slice of the updated coefficient need be used to perform the filtering and yet provide adequate precision. Description of an architecture of a word-slice digital signal processor and applications to adaptive equalization and automatic gain control are provided.

Abstract: Method and apparatus for processing digital signals represented as binary words, employing a portion of each word (a "slice") to afford appropriate accuracy. Particularly suited to medium- to high-speed telecommunications applications. In an exemplary transversal filtering operation application, only the high-order slice of the updated coefficient need be used to perform the filtering and yet provide adequate precision. Description of an architecture of a word-slice digital signal processor and applications to adaptive equalization and automatic gain control are provided.