Patents by Inventor Sagar Magia

Sagar Magia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10032524
    Abstract: Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 24, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Jagdish Sabde, Sagar Magia, Jayavel Pachamuthu
  • Patent number: 9934872
    Abstract: Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 3, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Sagar Magia, Jagdish Sabde, Jayavel Pachamuthu
  • Patent number: 9830998
    Abstract: A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Sagar Magia, Ankitkumar Babariya, Jagdish Sabde
  • Patent number: 9653175
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 16, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Jagdish Sabde, Sagar Magia, Khanh Nguyen
  • Patent number: 9564219
    Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 7, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Sagar Magia, Jagdish Sabde, Jayavel Pachamuthu, Ankitkumar Babariya
  • Publication number: 20170025182
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Application
    Filed: October 3, 2016
    Publication date: January 26, 2017
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Jagdish Sabde, Sagar Magia, Khanh Nguyen
  • Patent number: 9548129
    Abstract: Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 17, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Rajan Paudel, Jagdish Sabde, Mrinal Kochar, Sagar Magia
  • Patent number: 9530514
    Abstract: Detecting defects in select gates of memory cell strings is disclosed. An electrical short between adjacent select gates may be detected. The select gate may comprises a transistor having an adjustable threshold voltage. An operation configured to change a threshold voltage of one select transistor and to maintain a threshold voltage of an adjacent select transistor may be performed. The select transistors may be flagged in response to the threshold voltage of either select transistor failing to meet a target threshold voltage in response to the operation. The operation may be an erase operation or a program operation.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Jagdish Sabde, Jayavel Pachamuthu, Sagar Magia
  • Patent number: 9514835
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: December 6, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Sagar Magia, Jagdish Sabde, Khanh Nguyen
  • Publication number: 20160343454
    Abstract: A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 24, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Jayavel Pachamuthu, Sagar Magia, Ankitkumar Babariya, Jagdish Sabde
  • Patent number: 9496040
    Abstract: A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of a multi-pass programming operation for the memory cell, wherein a first set of program pulses is applied to the selected word line during the one programming pass, determining a number of the program pulses applied to the selected word line during the one programming pass, determining a difference between the determined number of program pulses applied to the selected word line during the one programming pass and a predetermined number of program pulses, adjusting a parameter of a second set of program pulses for the another programming pass based on the determined difference, and performing the another programming pass for the set of memory cells, wherein the second set of program pulses is applied to the selected word line during the another programming pass.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: November 15, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia
  • Patent number: 9484086
    Abstract: A number of techniques determine defects in non-volatile memory arrays, which are particularly applicable to 3D NAND memory, such as BiCS type. Word line to word line shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used to determine word line to word line leaks between different blocks. Select gate leak line leakage, for both the word lines and other select lines, is considered, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques determine shorts between bit lines and low voltage circuitry, such as in sense amplifiers.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: November 1, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Sagar Magia, Jagdish M. Sabde
  • Publication number: 20160300607
    Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 13, 2016
    Inventors: Sagar Magia, Jagdish Sabde, Jayavel Pachamuthu, Ankitkumar Babariya
  • Patent number: 9460809
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: October 4, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Sagar Magia, Jagdish Sabde
  • Patent number: 9449698
    Abstract: Techniques are provided for erasing a memory device. In one aspect, different zones of a block can be separately erased and subject to a verify test. Erase parameters can be optimized for each zone, so that endurance is improved. If one zone is found to be too slow to erase, it can be marked as being bad while other zones remain available for use. In another aspect, the zone-based erase occurs after a block based erased when a criterion is met, such as the block-based erase being too slow or failing to complete within an allowable number of program loops. The zone-based erase can occur after the block-based erase in the same erase operation, or in a subsequent, new erase operation.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: September 20, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia
  • Patent number: 9449694
    Abstract: A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: September 20, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia, Khanh Nguyen
  • Patent number: 9443612
    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jagdish M. Sbade, Sagar Magia
  • Publication number: 20160260495
    Abstract: Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.
    Type: Application
    Filed: October 21, 2015
    Publication date: September 8, 2016
    Applicant: SanDisk Technologies Inc.
    Inventors: Rajan Paudel, Jagdish Sabde, Mrinal Kochar, Sagar Magia
  • Publication number: 20160232985
    Abstract: Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.
    Type: Application
    Filed: May 14, 2015
    Publication date: August 11, 2016
    Inventors: Jagdish Sabde, Sagar Magia, Jayavel Pachamuthu
  • Publication number: 20160217857
    Abstract: A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of a multi-pass programming operation for the memory cell, wherein a first set of program pulses is applied to the selected word line during the one programming pass, determining a number of the program pulses applied to the selected word line during the one programming pass, determining a difference between the determined number of program pulses applied to the selected word line during the one programming pass and a predetermined number of program pulses, adjusting a parameter of a second set of program pulses for the another programming pass based on the determined difference, and performing the another programming pass for the set of memory cells, wherein the second set of program pulses is applied to the selected word line during the another programming pass.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 28, 2016
    Applicant: SanDisk Technologies Inc.
    Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia