Abstract: Some implementations described herein provide apparatuses and techniques for correcting a network disruption during a virtual meeting. In response to detecting audio and/or video input to a first device, audio and/or video data is recorded and stored in a temporary buffer of the first device. After the network disruption, and using time stamps, a network disruption server may request the audio and/or video data from the first device and transmit the audio and/or video data to a second device at an accelerated rate.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a field effect transistor (FET). The FET includes a source/drain (S/D) epitaxy and a metal gate. Additionally, the semiconductor structure includes a backside epitaxy in electrical contact with the S/D epitaxy. Further, the backside epitaxy includes a highly doped epitaxy. Additionally, the semiconductor structure includes a backside contact in electrical contact with the backside epitaxy. Further, the semiconductor structure includes a backside power distribution network in electrical contact with the backside contact.

Abstract: A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, a first silicide liner directly beneath the first source drain region, and second silicide liner directly beneath the second source drain region, where the first silicide liner is a different material than the second silicide liner.

Abstract: A semiconductor structure is provided that includes a first stacked FET cell including a second FET stacked over a first FET, and a second stacked FET cell located adjacent to the first stacked FET cell and including a fourth FET stacked over a third FET. The structure further includes a first backside source/drain contact structure located beneath the first stacked FET cell and contacting a source/drain region of the first FET, a second backside source/drain contact structure located beneath the second stacked FET cell and contacting a source/drain region of the third FET, and an angled cut region laterally separating the first backside source/drain contact structure from the second backside source/drain contact structure.

Abstract: A semiconductor IC device includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region that separates active regions. The connection may include a faux S/D region between a frontside contact and a backside contact. The semiconductor IC device may further include a first and/or second diffusion break isolation rail. The connection may be between the first and second diffusion break isolation rails. The connection location within the DDB region may resultantly increase packing densities of the semiconductor IC device. Further, the connection may reduce routing complexities and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Further, the connection may utilize mirrored structure instances (e.g., frontside contact, backside contact, faux S/D region, or the like) as that are used by microdevices (e.g., transistors, or the like) within the active regions, which may decrease fabrication complexities.

Abstract: A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. A method of forming the same is also provided.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.

Abstract: A structure that includes a substrate and a nanofilter formed on the substrate, wherein the nanofilter is adapted to allow nanoparticles of a predetermined size to pass through the nanofilter.

Abstract: A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.

Abstract: Some implementations described herein provide apparatuses and techniques for correcting a network disruption during a virtual meeting. In response to detecting audio and/or video input to a first device, audio and/or video data is recorded and stored in a temporary buffer of the first device. After the network disruption, and using time stamps, a network disruption server may request the audio and/or video data from the first device and transmit the audio and/or video data to a second device at an accelerated rate.

Abstract: One or more embodiments includes a semiconductor device. The semiconductor device includes: a first Gate-All-Around (GAA) field-effect transistor (FET) disposed on a silicon layer; and a second GAA FET disposed on the silicon layer adjacent to the first GAA FET. The semiconductor device also includes: an isolation layer disposed within the silicon layer between a first bottom dielectric isolation (BDI) layer of the first GAA FET and a second BDI layer of the second GAA FET; and a gate structure disposed proximate the first GAA FET and the second GAA FET, wherein at least one of a cap or a sidewall spacer isolates the gate structure from the silicon layer.

Abstract: A semiconductor structure includes a frontside source/drain region, and a dielectric stack disposed on a bottom surface of the frontside source/drain region. The dielectric stack includes a first dielectric layer and a second dielectric layer.

Abstract: A semiconductor structure is provided that includes a stress modulating pattern containing bonding dielectric layer. The stress modulating pattern containing bonding dielectric layer can be formed on a wafer, on a device-containing region that is present on a device wafer, or both a wafer and a device-containing region that is present on a device wafer. The stress modulating pattern is composed of a plurality of patterned structures (metal and/or dielectric) that are embedded at least partially within a bonding dielectric layer. Warpage modulation can be achieved using such a stress modulating pattern containing bonding dielectric layer.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first nanosheet device including a plurality of active semiconductor layers, a first metal stack wrapping around the active semiconductor layers, and a first gate insulator layer between the active semiconductor layers and the first metal stack; and a second nanosheet device including a second metal contact, the first metal stack wrapping around the second metal contact, and a second gate insulator between the second metal contact and the first metal stack.

Abstract: A semiconductor structure includes a nanosheet channel stack disposed on a semiconductor substrate. The nanosheet channel stack includes one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate. The semiconductor structure further includes an epitaxial oxide spacer layer disposed on outer ends of a bottom surface of the insulator layer and extending downwardly into the substrate; shallow trench isolation regions disposed adjacent the nanosheet channel stack and extending downwardly from a top surface of the semiconductor substrate, wherein a portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer; and a gate surrounding the nanosheet channel stack and on a top surface of each of the shallow trench isolation regions.

Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect transistor (FET) region, a second FET region and a backside signal distribution network (BSSDN). The first FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends through the STI and the ILD. The second FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends to the STI. The BSSDN is disposed on the ILD in the first and second regions to contact with the contact in the first FET region.

Abstract: Stream alterations under limited bandwidth conditions is provided. A router on a local network continuously monitors incoming network traffic from a source external to the local network to detect that a bandwidth of the incoming network traffic exceeds a first threshold. The router sends a request to a source of the incoming network traffic to temporarily redirect the incoming network traffic to an optimization analyzer. Analysis is performed on the incoming streams to identify one or more streams for alteration. In response to identifying one or more of the incoming streams for alteration, for each identified incoming stream, continuously altering the identified incoming stream, and re-directing the altered stream to the local device.

Abstract: A neural lattice device includes a substrate having formed therein one or more wells and one or more supply ducts. A channel network includes one or more channels configured to establish fluid communication among the at least one well and the at least one supply duct. A reservoir is coupled to the substrate and configured to hold a fluid, and a cover is disposed against an upper surface of the substrate and configured to hermetically seal the wells, the supply ducts and the channel network.

Abstract: A semiconductor structure includes a source/drain region; a frontside source/drain contact disposed on the source/drain region, a via-to-backside power rail disposed on the frontside source/drain contact and on a portion of the source/drain region, and a backside power rail connected to the via-to-backside power rail.