Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.

Abstract: A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.

Abstract: Stream alterations under limited bandwidth conditions is provided. A router on a local network continuously monitors incoming network traffic from a source external to the local network to detect that a bandwidth of the incoming network traffic exceeds a first threshold. The router sends a request to a source of the incoming network traffic to temporarily redirect the incoming network traffic to an optimization analyzer. Analysis is performed on the incoming streams to identify one or more streams for alteration. In response to identifying one or more of the incoming streams for alteration, for each identified incoming stream, continuously altering the identified incoming stream, and re-directing the altered stream to the local device.

Abstract: A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Abstract: A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Abstract: Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting Majorana fermions and a quantum well tunable Josephson junction that is coupled to the control components.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer walls on the opposed vertical walls of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer wails on the opposed vertical wails of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

Abstract: Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting Majorana fermions and a quantum well tunable Josephson junction that is coupled to the control components.

Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.

Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: The disclosure relates to implant systems and methods for stimulation of the cochlea, auditory nerve, and/or vestibular system using an intra-cochlear magnetic stimulation electrode array that uses targeted magnetic stimulation to induce neural activation without the need for mechanical transduction. The magnetic field produced by the array stimulates portions of the cochlea or provides signals to the vestibular system.