Patents by Inventor Sagheer Ahmad

Sagheer Ahmad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11327899
    Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh
  • Patent number: 11281618
    Abstract: A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 22, 2022
    Assignee: XLNX, INC.
    Inventors: Sagheer Ahmad, Tomai Knopp
  • Patent number: 11263169
    Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: March 1, 2022
    Assignee: XILINX, INC.
    Inventors: Ian Andrew Swarbrick, Sagheer Ahmad, Ygal Arbel, Dinesh Gaitonde
  • Patent number: 11182110
    Abstract: A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 23, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Sagheer Ahmad
  • Publication number: 20210303509
    Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
    Type: Application
    Filed: November 16, 2020
    Publication date: September 30, 2021
    Inventors: Ian Andrew SWARBRICK, Sagheer AHMAD, Ygal ARBEL, Dinesh GAITONDE
  • Patent number: 11063594
    Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Publication number: 20210124711
    Abstract: An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Applicant: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Sagheer Ahmad
  • Patent number: 10916516
    Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to a qualified stacked silicon interconnect (SSI) technology programmable integrated circuit (IC) region by providing an interface (e.g., an HBM buffer region implemented with a hierarchical switch network) between the added feature device and the programmable IC region. One example apparatus generally includes a programmable IC region and an interface region configured to couple the programmable IC region to at least one fixed feature die via a first plurality of ports associated with the at least one fixed feature die and a second plurality of ports associated with the programmable IC region. The interface region is configured as a switch network between the first plurality of ports and the second plurality of ports, and the switch network includes a plurality of full crossbar switch networks.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 9, 2021
    Assignee: XILINX, INC.
    Inventors: Martin Newman, Sagheer Ahmad
  • Patent number: 10838908
    Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: November 17, 2020
    Assignee: XILINX, INC.
    Inventors: Ian A. Swarbrick, Sagheer Ahmad, Ygal Arbel, Dinesh D. Gaitonde
  • Patent number: 10817455
    Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: October 27, 2020
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, Sagheer Ahmad, Ian A. Swarbrick
  • Publication number: 20200327089
    Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaideep Dastidar, Sagheer Ahmad, Ian A. Swarbrick
  • Patent number: 10719452
    Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh
  • Patent number: 10698842
    Abstract: Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 30, 2020
    Assignee: XILINX, INC.
    Inventors: Jaideep Dastidar, Sagheer Ahmad
  • Patent number: 10673745
    Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: XILINX, INC.
    Inventors: Ian A. Swarbrick, Ygal Arbel, Millind Mittal, Sagheer Ahmad
  • Patent number: 10673439
    Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 2, 2020
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Publication number: 20200026684
    Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 23, 2020
    Applicant: Xilinx, Inc.
    Inventors: Ian A. Swarbrick, Sagheer Ahmad, Ygal Arbel, Dinesh D. Gaitonde
  • Publication number: 20190391929
    Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh
  • Patent number: 10410694
    Abstract: Techniques related to a high bandwidth interface (HBI) for communication between multiple host devices on an interposer are described. In an example, the HBI repurposes a portion of the high bandwidth memory (HBM) interface, such as the physical layer. A computing system is provided. The computing system includes a first host device and at least a second host device. The first host device is a first die on an interposer and the second host device is a second die on the interposer. The first host device and the second host device are interconnected via at least one HBI. The HBI implements a layered protocol for communication between the first host device and the second host device. The layered protocol includes a physical layer protocol that is configured according to a HBM physical layer protocol.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 10, 2019
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Balakrishna Jayadev
  • Publication number: 20190250853
    Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.
    Type: Application
    Filed: February 15, 2018
    Publication date: August 15, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ygal Arbel, Ian A. Swarbrick, Sagheer Ahmad
  • Publication number: 20190238453
    Abstract: An example method of generating a configuration for a network on chip (NoC) in a programmable device includes: receiving traffic flow requirements for a plurality of traffic flows; assigning routes through the NoC for each traffic flow based on the traffic flow requirements; determining arbitration settings for the traffic flows along the assigned routes; generating programming data for the NoC; and loading the programming data to the programmable device to configure the NoC.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ian A. Swarbrick, Ygal Arbel, Millind Mittal, Sagheer Ahmad