Patents by Inventor Sagheer Ahmad

Sagheer Ahmad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261603
    Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: March 25, 2025
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Publication number: 20250080716
    Abstract: Some examples described herein provide for display image data reliability and safety, for example end-to-end safety methods, apparatuses, and systems for display systems. One example includes a method, including replacing video frames from input video streams with a set of test frames. The method further includes generating an alpha-blended video stream based on the set of test frames and the input video streams. The method further includes generating and inserting cyclic redundancy check (CRC) information for the set of test frames into secondary data packets associated with the alpha-blended video stream. The method further includes processing the set of test frames and video frames by a display controller to generate an output video stream. The method further includes performing an error detection procedure for the set of test frames using the CRC information to detect an error associated with the set of video frames.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Yanran CHEN, Roger MAY, Sagheer AHMAD, Qingyi SHENG, Krishnan SRINIVASAN, Vishal SAGAR, Pramod BHARDWAJ, Yashu GOSAIN
  • Patent number: 12244518
    Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 4, 2025
    Assignee: Xilinx, Inc.
    Inventors: Krishnan Srinivasan, Sagheer Ahmad, Ygal Arbel, Aman Gupta
  • Patent number: 12235782
    Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventors: Aman Gupta, Krishnan Srinivasan, Ahmad R. Ansari, Sagheer Ahmad
  • Patent number: 12237287
    Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Kenneth Ma, Balakrishna Jayadev, Sagheer Ahmad
  • Patent number: 12223355
    Abstract: Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 11, 2025
    Assignee: Xilinx, Inc.
    Inventors: Karthik Shankar, Jaideep Dastidar, Ahmad R. Ansari, Sagheer Ahmad
  • Publication number: 20240411715
    Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.
    Type: Application
    Filed: August 16, 2024
    Publication date: December 12, 2024
    Inventors: Krishnan SRINIVASAN, Sagheer AHMAD, Ygal ARBEL, Millind MITTAL
  • Publication number: 20240403253
    Abstract: Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Aman GUPTA, Krishnan SRINIVASAN, Brian C. GAIDE, Ahmad R. ANSARI, Sagheer AHMAD
  • Publication number: 20240387388
    Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: Brian C. GAIDE, Sagheer AHMAD, Aman GUPTA
  • Patent number: 12111784
    Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: October 8, 2024
    Assignee: XILINX, INC.
    Inventors: Krishnan Srinivasan, Abbas Morshed, Sagheer Ahmad
  • Publication number: 20240313781
    Abstract: Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Inventors: Brian C. GAIDE, Sagheer AHMAD, Trevor J. BAUER, Kenneth MA, David P. SCHULTZ, John O'DWYER, Richard W. SWANSON, Bhuvanachandran K. NAIR, Millind MITTAL
  • Patent number: 12093394
    Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: September 17, 2024
    Assignee: XILINX, INC.
    Inventors: Aman Gupta, James D. Wesselkamper, James Anderson, Nader Sharifi, Ahmad R. Ansari, Sagheer Ahmad, Brian C. Gaide
  • Publication number: 20240281537
    Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.
    Type: Application
    Filed: February 20, 2023
    Publication date: August 22, 2024
    Inventors: Aman GUPTA, James D. WESSELKAMPER, James ANDERSON, Nader SHARIFI, Ahmad R. ANSARI, Sagheer AHMAD, Brian C. GAIDE
  • Patent number: 12066969
    Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: August 20, 2024
    Assignee: XILINX, INC.
    Inventors: Krishnan Srinivasan, Sagheer Ahmad, Ygal Arbel, Millind Mittal
  • Patent number: 12047275
    Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: July 23, 2024
    Assignee: XILINX, INC.
    Inventors: Aman Gupta, Jaideep Dastidar, Jeffrey Cuppett, Sagheer Ahmad
  • Publication number: 20240211422
    Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Aman GUPTA, Krishnan SRINIVASAN, Ahmad R. ANSARI, Sagheer AHMAD
  • Publication number: 20240211138
    Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Xilinx, Inc.
    Inventors: Aman Gupta, Krishnan Srinivasan, Shishir Kumar, Sagheer Ahmad, Ahmad R. Ansari
  • Patent number: 12019908
    Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: June 25, 2024
    Assignee: XILINX, INC.
    Inventors: Krishnan Srinivasan, Shishir Kumar, Sagheer Ahmad, Abbas Morshed, Aman Gupta
  • Patent number: 12019576
    Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: June 25, 2024
    Assignee: XILINX, INC.
    Inventors: Krishnan Srinivasan, Ygal Arbel, Sagheer Ahmad, Abbas Morshed
  • Publication number: 20240176758
    Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Krishnan SRINIVASAN, Ygal ARBEL, Sagheer AHMAD