Patents by Inventor Sahil Patel
Sahil Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956971Abstract: A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.Type: GrantFiled: September 21, 2020Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huanlong Liu, Guenole Jan, Ru-Ying Tong, Jian Zhu, Yuan-Jen Lee, Jodi Mari Iwata, Sahil Patel, Vignesh Sundar
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Patent number: 11903324Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.Type: GrantFiled: July 26, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
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Publication number: 20230389441Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Applicant: Applied Materials, Inc.Inventors: Minrui YU, Wenhui WANG, Jaesoo AHN, Jong Mun KIM, Sahil PATEL, Lin XUE, Chando PARK, Mahendra PAKALA, Chentsau Chris YING, Huixiong DAI, Christopher S. NGAI
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Patent number: 11723283Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.Type: GrantFiled: May 11, 2020Date of Patent: August 8, 2023Assignee: Applied Materials, Inc.Inventors: Minrui Yu, Wenhui Wang, Jaesoo Ahn, Jong Mun Kim, Sahil Patel, Lin Xue, Chando Park, Mahendra Pakala, Chentsau Chris Ying, Huixiong Dai, Christopher S. Ngai
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Publication number: 20230217834Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.Type: ApplicationFiled: March 10, 2023Publication date: July 6, 2023Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
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Patent number: 11696511Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.Type: GrantFiled: October 5, 2020Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sahil Patel, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Dongna Shen, Yu-Jen Wang, Po-Kang Wang, Huanlong Liu
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Publication number: 20230159268Abstract: A waste management receptacle system for containment of odorous waste comprising a primary receptacle, comprising a base with vertically extending sidewalls forming an interior portion, a rim, and primary receptacle lid movable between an open and closed position. The system includes a secondary receptacle comprising a bottom with upstanding sidewalls forming a secondary interior, and a lid portion moveable between open and closed positions. A clamping member secures the secondary receptacle within the primary receptacle interior. The clamping member comprises a lateral member having ends with longitudinal members extending therefrom, and a fastening member disposed on a longitudinal member. The fastening member is movable between a disengaged and engaged position to secure the clamping member to the primary receptacle.Type: ApplicationFiled: November 15, 2022Publication date: May 25, 2023Inventors: Sahil Patel, Ashish Patel
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Patent number: 11631802Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.Type: GrantFiled: November 7, 2019Date of Patent: April 18, 2023Assignee: Headway Technologies, Inc.Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
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Patent number: 11597993Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10?6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance×area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.Type: GrantFiled: May 10, 2021Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sahil Patel, Guenole Jan, Yu-Jen Wang
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Patent number: 11522126Abstract: A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.Type: GrantFiled: October 14, 2019Date of Patent: December 6, 2022Assignee: Applied Materials, Inc.Inventors: Lin Xue, Jaesoo Ahn, Sahil Patel, Chando Park, Mahendra Pakala
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Publication number: 20220384718Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.Type: ApplicationFiled: July 27, 2022Publication date: December 1, 2022Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
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Publication number: 20220359821Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
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Patent number: 11424405Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.Type: GrantFiled: June 29, 2020Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
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Patent number: 11411174Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.Type: GrantFiled: December 18, 2019Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
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Publication number: 20220134985Abstract: A radiator protection device that protects a vehicle radiator from debris and damage is disclosed. The device is a multi-layer system that is flexible enough to be installed and removed through the radiator grill or other openings into the vehicle's radiator compartment. Installed configuration requires no mounting features nor support provisions due to the nature of fitment and resiliency of device to return to original shape.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventor: Sahil Patel
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Patent number: 11317570Abstract: The present disclosure provides peanut maturity grading systems and methods for quickly, efficiently, and objectively determining a peanut maturity grade for a crop of peanuts and determining an optimal harvest time for the crop. Embodiments of systems and methods of the present disclosure can be performed in the field or field-side and do not require assistance of a trained peanut grading specialist.Type: GrantFiled: September 5, 2019Date of Patent: May 3, 2022Assignee: University of Georgia Research Foundation, Inc.Inventors: Tsz Ho Tse, Brian Boland, Donald Leo, Kyle Johnsen, Sahil Patel, Zhuo Zhao
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Patent number: 11316103Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.Type: GrantFiled: December 27, 2019Date of Patent: April 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dongna Shen, Yu-Jen Wang, Ru-Ying Tong, Vignesh Sundar, Sahil Patel
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Patent number: 11289645Abstract: A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.Type: GrantFiled: December 31, 2018Date of Patent: March 29, 2022Assignee: Headway Technologies, Inc.Inventors: Yi Yang, Vignesh Sundar, Dongna Shen, Sahil Patel, Ru-Ying Tong, Yu-Jen Wang
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Publication number: 20210351342Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Inventors: Minrui YUI, Wenhui WANG, Jaesoo AHN, Jong Mun KIM, Sahil PATEL, Lin XUE, Chando PARK, Mahendra PAKALA, Chentsau Chris YING, Huixiong DAI, Christopher S. Ngai
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Publication number: 20210262078Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10?6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance×area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Sahil Patel, Guenole Jan, Yu-Jen Wang