Patents by Inventor Sahil Sharma

Sahil Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817187
    Abstract: In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool trans
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 27, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Publication number: 20200279611
    Abstract: Disclosed is an apparatus including a memory device. The memory device includes a memory array, a number of non-volatile memory sections configured to store a copy of operational information for the memory array, and a controller coupled to the number of non-volatile memory sections. The controller can responsive to a first wake-up operation, select a first non-volatile memory section as a starting section to retrieve the copy of operational information. The controller can responsive to a second wake-up operation, select a second non-volatile memory section as the starting section to retrieve the copy of operational information without regard to success of a prior attempt to retrieve the copy of operational information.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Phil Reusswig, Sahil Sharma, Gautam Dusija
  • Publication number: 20200258584
    Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Niles Yang
  • Publication number: 20200258582
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Sahil SHARMA, Nian YANG, Philip David REUSSWIG
  • Patent number: 10741261
    Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 11, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Niles Yang
  • Patent number: 10743392
    Abstract: Disclosed are systems and methods for cloud-based monitoring and control of physical environments. In various embodiments, a computing device (1350, 1450, 1550) seeking to verify credentials of a lighting system controller (1352, 1452, 1552) may obtain unverified credentials of the lighting system controller. The computing device may transmit, to a first remote device via a first network communication channel, a request to verify the unverified credentials. The computing device may receive verification from the first remote device or a second remote device via a second network communication channel. The second network communication channel may be different than the first network communication channel. The computing device may compare the unverified credentials to the verification data and verify, based on the comparing, that the unverified credentials are legitimate.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: August 11, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Sahil Sharma, Sandeep Shankaran Kumar, Mark Henricus Verberkt
  • Patent number: 10732864
    Abstract: A data storage device includes a power input port, a nonvolatile memory module, a controller for the nonvolatile memory module, and a power analyzer electrically coupled to the power input port. The power analyzer is configured to receive input power from the power input port, determine power data associated with the data storage device based on the input power, and store the power data in a memory of the power analyzer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Sahil Sharma
  • Publication number: 20200241765
    Abstract: In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool trans
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Publication number: 20200226065
    Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Patent number: 10714169
    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Phil Reusswig, Pitamber Shukla, Sarath Puthenthermadam, Mohan Dunga, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Patent number: 10706936
    Abstract: In one embodiment, there is a system comprising a first group of blocks connected to a first address line, a second group of blocks connected to a second address line separate and distinct from the first address line, a host controller (or memory device) configured to: allocate a single open block to each of: the first group of blocks connected to the first address line that transmits an address signal generated by a first peripheral circuitry module, and the second group of blocks connected to the second address line that transmits an address signal generated by a second peripheral circuitry module; in response to receiving a first program request: program the open block in the first group of blocks connected to the first address line in response to a first program request in response to receiving a second program request separate and distinct from the first program request: forego programming any of the blocks in the first group of blocks connected to the first address line; and program one of the blocks in
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rohit Sehgal, Grishma Shah, Sahil Sharma, Phil Reusswig
  • Publication number: 20200192791
    Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Sahil Sharma, Philip Reusswig, Rohit Sehgal
  • Patent number: 10685722
    Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 16, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Niles Yang
  • Patent number: 10679708
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 9, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
  • Patent number: 10658045
    Abstract: A method for programming memory blocks in a memory system includes identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system. The method also includes performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks. The method also includes storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks. The method also includes identifying, using the pre-erase table, at least one memory block to be programmed. The method also includes programming the at least one memory block by performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and performing a write operation on the at least one memory block.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 19, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Publication number: 20200090759
    Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Inventors: Sahil SHARMA, Nian Yang, Philip David Reusswig
  • Patent number: 10573397
    Abstract: On a non-volatile memory circuit, peripheral circuitry generates programming voltages based on parameter values. If parameter values are incorrectly translated into programming voltages, data may be over-programmed, resulting in high bit error rates (BERs). The memory system can monitor the error rates using memory cell voltage distributions for different portions of the memory and look for signatures of such incorrect implementation. For example, by monitoring the BER along word lines that are most prone to error due to incorrectly implemented programming parameters, the memory system can determine if the programming parameters for the corresponding portion of a memory device indicate such anomalous behavior. If such a signature is found, the memory system checks to see whether the programming parameters should be adjusted, such as by comparing the programming parameters used on one die to programming parameters used on another die of the memory system, and adjust the programming parameters accordingly.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rohit Sehgal, Sahil Sharma, Philip Reusswig, Nian Niles Yang
  • Publication number: 20190188579
    Abstract: Methods and systems for using machine learning to automatically determine a data loading configuration for a computer-based rule engine are presented. The computer-based rule engine is configured to use rules to evaluate incoming transaction requests. Data of various data types may be required by the rule engine when evaluating the incoming transaction requests. The data loading configuration specifies pre-loading data associated with at least a first data type and lazy-loading data associated with at least a second data type. Statistical data such as use rates and loading times associated with the various data types may be supplied to a machine learning module to determine a particular loading configuration for the various data types. The computer-based rule engine then loads data according to the data loading configuration when evaluating a subsequent transaction request.
    Type: Application
    Filed: March 30, 2018
    Publication date: June 20, 2019
    Inventors: Srinivasan Manoharan, Vinesh Chirakkil, Jun Zhu, Christopher S. Purdum, Sahil Dahiya, Gurinder Grewal, Harish Nalagandla, Girish Sharma
  • Publication number: 20190188578
    Abstract: Methods and systems for automatically discovering data types required by a computer-based rule engine for evaluating a transaction request are presented. Multiple potential paths for evaluating the transaction request according to the rule engine are determined. An abstract syntax tree may be generated based on the rule engine to determine the multiple potential paths. Based on an initial set of data extracted from the transaction request, one or more potential paths that are determined to be irrelevant to evaluating the transaction request are identified. Types of data required to evaluate the transaction request according to the remaining potential paths are determined. Only data that corresponds to the determined types of data is retrieved to evaluate the transaction request.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: Srinivasan Manoharan, Sahil Dahiya, Vinesh Chirakkil, Gurinder Grewal, Harish Nalagandla, Christopher S. Purdum, Girish Sharma
  • Publication number: 20190132931
    Abstract: Disclosed are systems and methods for cloud-based monitoring and control of physical environments. In various embodiments, a computing device (1350, 1450, 1550) seeking to verify credentials of a lighting system controller (1352, 1452, 1552) may obtain unverified credentials of the lighting system controller. The computing device may transmit, to a first remote device via a first network communication channel, a request to verify the unverified credentials. The computing device may receive verification from the first remote device or a second remote device via a second network communication channel. The second network communication channel may be different than the first network communication channel. The computing device may compare the unverified credentials to the verification data and verify, based on the comparing, that the unverified credentials are legitimate.
    Type: Application
    Filed: April 12, 2017
    Publication date: May 2, 2019
    Applicant: PHILIPS LIGHTING HOLDING B.V.
    Inventors: SAHIL SHARMA, SANDEEP SHANKARAN KUMAR, MARK HENRICUS VERBERKT