Patents by Inventor Sahil Sharma
Sahil Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11354190Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.Type: GrantFiled: February 24, 2021Date of Patent: June 7, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Rohit Sehgal, Sahil Sharma, Nian Niles Yang, Philip David Reusswig
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Patent number: 11334256Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.Type: GrantFiled: February 3, 2020Date of Patent: May 17, 2022Assignee: Western Digital Technologies, Inc.Inventors: Sahil Sharma, Nian Niles Yang, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre
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Publication number: 20220129055Abstract: The present disclosure generally relates to efficient block usage after ungraceful shutdown (UGSD) events. After a UGSD event, a host device is alerted by the data storage device that a QLC block that was being used prior to the UGSD event is experiencing an ongoing block recovery and that the block is not yet available to accept new data. The block is then checked to determine whether the block can continue to be used for the programming that was occurring at the time of the UGSD event. Once a determination is made, the data storage device notifies the host device so that normal operations may continue. Additionally, the amount of free blocks available for programming is monitored during UGSD events so that the host device can be warned if a power loss halt is triggered.Type: ApplicationFiled: February 24, 2021Publication date: April 28, 2022Inventors: Nian Niles YANG, Sahil SHARMA, Judah Gamliel HAHN
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Publication number: 20220076249Abstract: Methods and systems are presented for creating and distributing blockchain-backed redistributable electronic content components. These techniques provider greater computer security and authentication controls, in various embodiments. An electronic content component associated with a first entity and a first set of actions is created. The electronic content component is published, and the first set of actions and a block representing the electronic content component are added to a blockchain. A second entity requests use of the electronic content component and a distribution agreement between the first and second entities associated with a second set of actions is created. The second set of actions and a block representing the distribution agreement are added to a blockchain. The electronic content component and distribution agreement are validated based on the blockchain, and custom content including the electronic content component is published.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Sahil Sharma, Ben William Gordon Hurst, Ping An, Purna Aditya Kumar Bhimaraju, Varun Kumar
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Publication number: 20220068423Abstract: A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.Type: ApplicationFiled: March 26, 2021Publication date: March 3, 2022Applicant: Western Digital Technologies, Inc.Inventors: Nian YANG, Sahil SHARMA, Harish SINGIDI
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Publication number: 20220050747Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.Type: ApplicationFiled: February 24, 2021Publication date: February 17, 2022Inventors: Rohit Sehgal, Sahil Sharma, Nian Niles Yang, Philip David Reusswig
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Patent number: 11211132Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.Type: GrantFiled: February 27, 2020Date of Patent: December 28, 2021Assignee: SanDisk Technologies LLCInventors: Piyush A. Dhotre, Sahil Sharma, Niles Yang, Phil Reusswig
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Patent number: 11210001Abstract: Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.Type: GrantFiled: April 22, 2020Date of Patent: December 28, 2021Assignee: Western Digital Technologies, Inc.Inventors: Niles Yang, Phil Reusswig, Sahil Sharma, Rohit Sehgal
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Publication number: 20210397505Abstract: The present disclosure generally relates to identifying read failures that enhanced post write/read (EPWR) would normally miss. After the last logical word line has been written, additional stress is added to each word line. More specifically, the gate bias channel pass read voltage for all unselected word lines is increased, the gate bias on dummy and selected gate word lines is increased, the gate bias on the selected word line is increased, and a pulse read occurs. The increasing and reading occurs for each word line. Thereafter, EPWR occurs. Due to the increasing and reading for every word line, additional read failures are discovered than would otherwise be discovered with EPWR alone.Type: ApplicationFiled: June 18, 2020Publication date: December 23, 2021Inventors: Piyush DHOTRE, Sahil SHARMA, Mrinal KOCHAR, Shantanu GUPTA
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Publication number: 20210389879Abstract: For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: SanDisk Technologies LLCInventors: Karin Inbar, Sahil Sharma, Grishma Shah
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Patent number: 11164634Abstract: A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell (“SLC”) memory cells or multi-level cell (“MLC”) memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the “nominal” programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.Type: GrantFiled: June 24, 2019Date of Patent: November 2, 2021Assignee: Western Digital Technologies, Inc.Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
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Publication number: 20210334030Abstract: Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Niles Yang, Phil Reusswig, Sahil Sharma, Rohit Sehgal
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Publication number: 20210272639Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.Type: ApplicationFiled: February 27, 2020Publication date: September 2, 2021Applicant: SanDisk Technologies LLCInventors: Piyush A. Dhotre, Sahil Sharma, Niles Yang, Phil Reusswig
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Publication number: 20210263821Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Applicant: Western Digital Technologies, Inc.Inventors: Nian Yang, Piyush Dhotre, Sahil Sharma
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Patent number: 11086643Abstract: A method and system monitors activity of a user of a data management system and detects a trigger event in the activity of the user. The method and system generates a support case responsive to the trigger event. The support case includes support rules defining what types of the user's personal data will be accessible to an assistance agent when the user requests assistance related to the trigger event. The method and system utilizes machine learning processes to determine what types of user related data should be accessible to assistance agents in support cases.Type: GrantFiled: November 28, 2018Date of Patent: August 10, 2021Assignee: Intuit Inc.Inventors: Sahil Sharma, Divya Kumar, Rajshekhar Desai, Bhargava Narayana, Arun Kumar A, Zeerak Mehdi
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Publication number: 20210240358Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.Type: ApplicationFiled: February 3, 2020Publication date: August 5, 2021Applicant: Western Digital Technologies, Inc.Inventors: Sahil Sharma, Nian Niles Yang, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre
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Patent number: 11081187Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.Type: GrantFiled: December 11, 2019Date of Patent: August 3, 2021Inventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre, Niles Yang
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Publication number: 20210183450Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.Type: ApplicationFiled: December 11, 2019Publication date: June 17, 2021Applicant: SanDisk Technologies LLCInventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre, Niles Yang
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Patent number: 11030096Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.Type: GrantFiled: January 10, 2019Date of Patent: June 8, 2021Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
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Patent number: 10998073Abstract: Disclosed is an apparatus including a memory device. The memory device includes a memory array, a number of non-volatile memory sections configured to store a copy of operational information for the memory array, and a controller coupled to the number of non-volatile memory sections. The controller can responsive to a first wake-up operation, select a first non-volatile memory section as a starting section to retrieve the copy of operational information. The controller can responsive to a second wake-up operation, select a second non-volatile memory section as the starting section to retrieve the copy of operational information without regard to success of a prior attempt to retrieve the copy of operational information.Type: GrantFiled: February 28, 2019Date of Patent: May 4, 2021Assignee: Western Digital Technologies, Inc.Inventors: Phil Reusswig, Sahil Sharma, Gautam Dusija