Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties.

Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties.

Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.

Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties.

Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.

Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties.

Abstract: A magnetoresistive random access memory architecture free of isolation devices includes a plurality of data columns of non-volatile magnetoresistive elements. A reference column includes non-volatile magnetoresistive elements positioned adjacent to the data column. Each column is connected to a current conveyor. A selected data current conveyor and the reference current conveyor are connected to inputs of a differential amplifier for differentially comparing a data voltage to a reference voltage. The current conveyors are connected directly to the ends of the data and reference bitlines. This specific arrangement allows the current conveyors to be clamped to the same voltage which reduces or removes sneak circuits to substantially reduce leakage currents.

Abstract: An improved and novel magnetic element (10; 10′; 50; 50′; 80) including a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field. Additionally disclosed is a method of fabricating a magnetic element (10) by providing a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields of the thin film layers cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field.

Abstract: A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (10) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (56) including a flux concentrating layer (52). The method includes the steps of depositing a bottom dielectric layer (32), an optional etch stop (34) layer, and a top dielectric layer (36) proximate the magnetic memory bit (10). A trench (38) is etched in the top dielectric layer (36) and the bottom dielectric layer (32). A first barrier layer (42) is deposited in the trench (38). Next, a metal system (29) is deposited on a surface of the first barrier layer (42). The metal system (29) includes a copper (Cu) seed material (44), and a plated copper (Cu) material (46), a first outside barrier layer (50), a flux concentrating layer (52), and a second outside barrier layer (54). The metal system (29) is patterned and etched to define a copper (Cu) damascene bit line (56).

Abstract: A multi-layer magnetic material (10) has magnetic vectors (21,22) that point along a length (27) of the material (10). Opposing magnetic fields cause the vectors to snap past the perpendicular position with a rapid change in the resistance of the material. The material is used as a memory cell (37,38,39,41) of a memory (36).

Abstract: An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

Abstract: An improved and novel fabrication method for magnetoresistive random access memory (MRAM) is provided. An MRAM device has memory elements and circuitry for managing the memory elements. The circuitry includes transistor (12a), digit line (29), etc., which are integrated on a substrate (11). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (53, 54). A dielectric layer (40, 41) is deposited on the circuit, and trenches (42, 43) are formed in the dielectric layer. A blanket layer (46), which includes magnetic layers (48, 49) and a non-magnetic layer (50) sandwiched by the magnetic layers, is deposited on dielectric layer (41) and in the trenches. Then, the blanket layer outside the trenches is removed and MRAM elements (53, 54) are formed in the trenches.

Abstract: A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

Abstract: A low switching field magnetoresistive tunneling junction memory cell including a first exchange coupled structure having a pair of magnetoresistive layers and an exchange interaction layer sandwiched therebetween so as to pin the magnetic vectors of the pair of layers anti-parallel, a second exchange coupled structure having a pair of magnetoresistive layers and an exchange interaction layer sandwiched therebetween so as to pin the magnetic vectors of the pair of layers anti-parallel, and electrically insulating material sandwiched between the first and second exchange coupled structures to form a magnetoresistive tunneling junction. Each of the first and second exchange coupled structures, and hence the memory cell, has no net magnetic moment.

Abstract: A low aspect ratio magnetoresistive tunneling junction memory cell includes two layers of magnetoresistive material separated by electrically insulating material so as to form a magnetoresistive tunneling junction. An exchange interaction layer is sandwiched between one layer of the junction and a third layer of magnetoresistive material so as to pin the magnetic vector of one layer of the junction anti-parallel to a magnetic vector in the third layer so that magnetostatic interaction between the junction layers is canceled and the magnetic vector of the one layer is free to move in either of the two directions parallel to the polarization axis. Antiferromagnetic material is positioned adjacent the third layer so as to fix the magnetic vector in the third layer uni-directionally parallel to the polarization axis.

Abstract: A low switching field magnetic tunneling junction memory cell including an antiferromagnetically coupled structure having first and second magnetoresistive layers of different thicknesses and a non-magnetic conducting layer sandwiched therebetween so that the magnetic vectors of the pair of layers are anti-parallel with no applied magnetic field, a magnetoresistive structure having a magnetic vector, and electrically insulating material sandwiched between the antiferromagnetically coupled structure and the magnetoresistive structure to form a magnetic tunneling junction.

Abstract: A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Abstract: An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

Abstract: A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).

Abstract: A low switching field multi-state, multi-layer magnetic memory cell including two layers of magnetic material stacked in parallel, overlying relationship and separated by a layer of non-magnetic material so as to form a portion of a multi-layer magnetic memory cell. The two layers of magnetic material being formed so that the width is less than the length and less than a width of magnetic domain walls within the two layers of magnetic material, setting a shape anisotropy easy axis along the length thereof. At least one of the two layers of magnetic material having a magnetic anisotropy generally parallel to the width of the layers of magnetic material.