Patents by Inventor Saikumar Jayaraman

Saikumar Jayaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260096368
    Abstract: Systems, components, and methods for wafer level semiconductor die singulation are provided. Die singulation of differently sized semiconductor dies can be accomplished without sacrificing certain semiconductor dies in favor of others.
    Type: Application
    Filed: September 27, 2024
    Publication date: April 2, 2026
    Inventors: Michael J. BAKER, Vidya JAYARAM, Albert S. LOPEZ, Preston T. MYERS, Saikumar JAYARAMAN
  • Publication number: 20260003144
    Abstract: An optical connector, a semiconductor assembly including the optical connector, a multi-chip package including the optical connector, and a method of making the optical connector. The optical connector includes: a first lid; and a second lid attached to the first lid to define a cavity therebetween. Individual ones of the first lid and the second lid include: a substrate having an inner surface facing the cavity, an outer surface opposite the inner surface, a first end and a second end, the first end to receive a corresponding waveguide therein; and a concave mirror on the substrate and having a reflective surface facing the cavity, wherein a straight linear optical axis is to extend between the reflective surface of the concave mirror and a photonic structure at an opposing one of said individual ones of the first lid and the second lid.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Applicant: Intel Corporation
    Inventors: Li Yuan, Dekang Chen, Feifei Cheng, Fan Fan, Saikumar Jayaraman, Kumar Abhishek Singh
  • Publication number: 20250362456
    Abstract: Architectures and methods for graded index (GRIN) lens expanded beam (EB) coupler for detachable fiber array unit (FAU) for use with a photonic integrated circuit (PIC). A system to optically couple a fiber optic array (FAU) to a PIC die includes a graded index (GRIN) lens to optically couple a single mode fiber (SMF) in the FAU to a waveguide in the PIC die. The GRIN lens has a first mode field diameter (MFD) that is a function of a spot size converter of the waveguide. The SMF is a conduit for optical light with a wavelength and a second MFD. The GRIN lens has a length that is a function of a predetermined whole number of periodic cycles of the wavelength.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 27, 2025
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Dekang Chen, Fan Fan, Ziyin Lin, Li Yuan, Zhichao Zhang, Saikumar Jayaraman, Kumar Abhishek Singh
  • Publication number: 20250306281
    Abstract: Embodiments disclosed herein comprise a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises a first glass material. In an embodiment, a lens is on the second surface of the substrate, and the lens comprises a second glass material. In an embodiment, a fiber is contacting the first surface of the substrate, and the fiber comprises a third glass material. In an embodiment, fiber is fused to the first surface of the substrate.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 2, 2025
    Inventors: Kumar Abhishek SINGH, Li YUAN, Saikumar JAYARAMAN, Tim Tri HOANG, Sergey Yuryevich SHUMARAYEV
  • Publication number: 20250306297
    Abstract: Various aspects may provide a device which may be provided in a package. The device may include a photonic integrated circuit, a lens arrangement, and an optical fiber arrangement. The optical fiber arrangement may optically couple the photonic integrated circuit and the lens arrangement. The lens arrangement may be configured to be optically couplable to an external lens arrangement that is aligned with and spaced apart from the lens arrangement of the device, such that an optical signal is transmissible between the lens arrangement of the device and the external lens arrangement.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 2, 2025
    Inventors: Todd COONS, Li YUAN, Saikumar JAYARAMAN, Kumar Abhishek SINGH, Bilas CHOWDHURY, Ziyin LIN, Shahin MANI
  • Publication number: 20250306287
    Abstract: An apparatus includes an optical fiber coupled with a photonic integrated circuit (PIC) die. A first optical feature is at an end face of the optical fiber. The first optical feature tapers in a first longitudinal direction from a first base end proximal to the end face to a first tapered end. A second optical feature is at a surface of the PIC die. The second optical feature tapers in a second longitudinal direction from a second base end proximal to the surface to a second tapered end. The first optical feature is adjacent to, and may be longitudinally aligned with or parallel to, the second optical feature.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Dekang Chen, Fan Fan, Zhichao Zhang, Saikumar Jayaraman, Kumar Abhishek Singh, Feifei Cheng
  • Publication number: 20250306304
    Abstract: An optical fiber housing comprises a first face, a second face opposite the first face, a first side, and a second side opposite the first side. The first face is spaced apart from the second face by a first distance. A plurality of optical fibers extends in a longitudinal direction between the first and second faces, and are laterally spaced apart across a transverse width of the first face between the first side and the second side. Each optical fiber comprises a diameter. A surface of the housing is orthogonal to the first face and the first side. A plurality of alignment features is on the surface stand off from a remainder of the surface by a height greater than the diameter. The alignment features extend a second distance in the longitudinal direction that is less than the first distance, and comprises a curved or V-shaped peripheral surface.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Ziyin Lin, Yang Wu, Fan Fan, Jianyong Mo, Peter Williams, Darren Vance, Saikumar Jayaraman, Kumar Abhishek Singh
  • Publication number: 20250306307
    Abstract: Embodiments disclosed herein include an apparatus with a first substrate, and a groove in a surface of the first substrate. In an embodiment, a fiber is in the groove, and a second substrate is over the first substrate and the fiber. In an embodiment, a porous metallic material is provided between the first substrate and the second substrate.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Inventors: Darren VANCE, Sufi AHMED, Peter WILLIAMS, Ziyin LIN, Saikumar JAYARAMAN, Kumar Abhishek SINGH
  • Publication number: 20250306313
    Abstract: Assemblies comprising semiconductor devices, heat spreaders, and fiber-based input output (IO) connections are provided. Methods of manufacturing assemblies comprising semiconductor devices, heat spreaders, and fiber-based input output (IO) connections are also provided.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Inventors: Kumar Abhishek SINGH, Feifei CHENG, Ziyin LIN, Saikumar JAYARAMAN, Peter A. WILLIAMS, Darren A. VANCE, Todd R. COONS, Abir DEB
  • Publication number: 20250306318
    Abstract: Expanded beam optical fibers, and methods of forming the same, are disclosed herein. In one example, an optical fiber includes a first optical fiber section with a photonic crystal fiber, a second optical fiber section with a mode field adapter fiber, and a third optical fiber section with a single mode fiber. The first optical fiber section is coupled to the second optical fiber section, and the second optical fiber section is coupled to the third optical fiber section.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Fan Fan, Jianyong Mo, Dekang Chen, Feifei Cheng, Liang Zhang, Kumar Abhishek Singh, Saikumar Jayaraman
  • Publication number: 20250306294
    Abstract: In the various aspects, an optical package includes an optical connector that is at least partially configured with a first thickness that is less than a second thickness of the optical package. The optical package includes an assembly platform, a photonic integrated circuit disposed on the assembly platform, and the optical connector includes a housing with a first section and a second section, and an attachment assembly. In an aspect, the first section of the housing is disposed proximally to an edge of the assembly platform and is coupled to the photonic integrated circuit in the optical package, and the second section of the housing is coupled to a fiber optic jumper, and the attachment assembly joins the second section to the first section and enables the second section to be detached from the first section.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 2, 2025
    Inventors: Li YUAN, Fan FAN, Kumar Abhishek SINGH, Saikumar JAYARAMAN, Feifei CHENG, Stephanie AROUH, Todd COONS, Wesley MORGAN
  • Publication number: 20250306302
    Abstract: Photonic IC packages, related devices and methods, are disclosed herein. In some embodiments, a photonic package may include a substrate including a dielectric material with conductive pathways; a photonic integrated circuit (PIC) having a first optical element, the PIC electrically coupled to the substrate; a connector including a fiber alignment structure; and a second optical element, wherein the second optical element is to expand and collimate an optical beam; and a fiber having a first end and an opposing second end, wherein the fiber is positioned in the fiber alignment structure, and wherein the first end of the fiber is optically coupled to the first optical element and the second end of the fiber is optically coupled to the second optical element.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Saikumar Jayaraman, Kumar Abhishek Singh, Feifei Cheng, Li Yuan
  • Publication number: 20250306285
    Abstract: An embodiment may include an apparatus comprising a substrate with a thickness between a first surface and a second surface, where the substrate comprises a glass layer and a hole into the first surface of the substrate and into the glass layer. In an embodiment, a depth of the hole is less than the thickness, and a lens is on the second surface of the substrate, where a first axial centerline of the hole is substantially coincident with a second axial centerline of the lens.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 2, 2025
    Inventors: Stephanie AROUH, Li YUAN, Fan FAN, Srikant NEKKANTY, Kumar Abhishek SINGH, Saikumar JAYARAMAN
  • Publication number: 20250306290
    Abstract: Embodiments disclosed herein comprise an apparatus with a substrate with a first surface, and a second surface that is recessed from the first surface. In an embodiment, the second surface is adjacent to an edge of the substrate. In an embodiment, a hole is in the second surface, and a groove is in the first surface. In an embodiment, a centerline of the groove passes over the hole.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Inventors: Fan FAN, Jianyong MO, Dekang CHEN, Feifei CHENG, Liang ZHANG, Ziyin LIN, Kumar Abhishek SINGH, Saikumar JAYARAMAN
  • Publication number: 20250306303
    Abstract: Photonic IC packages, related devices and methods, are disclosed herein. In some embodiments, a photonic package may include a substrate; a photonic integrated circuit (PIC) having a first optical element, the PIC coupled to the substrate; a connector including a fiber alignment structure; and a second optical element, wherein the second optical element is to expand and collimate an optical beam, and wherein a material of the connector includes a 3-dimensional (3D) printing optical polymer, a 3D printing grade glass, a 3D printing optical resin, a fused silica glass, or an optical grade polymer; and a fiber having a first end and an opposing second end, wherein the fiber is positioned in the fiber alignment structure, and wherein the first end of the fiber is optically coupled to the first optical element and the second end of the fiber is optically coupled to the second optical element.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Li Yuan, Ziyin Lin, Kumar Abhishek Singh, Saikumar Jayaraman
  • Patent number: 12341281
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 24, 2025
    Assignee: Intel Corporation
    Inventors: Srikant Nekkanty, Debendra Mallik, Joe F. Walczyk, Saikumar Jayaraman, Feroz Mohammad
  • Publication number: 20250110295
    Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Saikumar Jayaraman, Yiqun Bai, Fan Fan, Dingying Xu
  • Publication number: 20250102744
    Abstract: Technologies for fiber array unit (FAU) lid designs are disclosed. In one embodiment, channels in the lid allow for suction to be applied to fibers that the lid covers, pulling the fibers into place in a V-groove. The suction can hold the fibers in place as the fiber array unit is mated with a photonic integrated circuit (PIC) die. Additionally or alternatively, channels can be on pitch, allowing for pulling the FAU towards a PIC die as well as sensing the position and alignment of the FAU to the PIC die. In another embodiment, a warpage amount of a PIC die is characterized, and a FAU lid with a similar warpage is fabricated, allowing for the FAU to position fibers correctly relative to waveguides in the PIC die. In another embodiment, a FAU has an extended lid, which can provide fiber protection as well as position and parallelism tolerance control.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kumar Abhishek Singh, Peter A. Williams, Ziyin Lin, Fan Fan, Yang Wu, Saikumar Jayaraman, Baris Bicen, Darren Vance, Anurag Tripathi, Divya Pratap, Stephanie J. Arouh
  • Publication number: 20250004223
    Abstract: An apparatus comprising an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (PIC).
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Xiaoqian Li, Vidya Jayaram, Ravindranath V. Mahajan, Saikumar Jayaraman
  • Patent number: 12088695
    Abstract: A first semiconductor device includes a processor configured to generate a random number at initial test of a second semiconductor device after fabrication of the second semiconductor device in a supply chain related to the second semiconductor device, and send the generated random number to the second semiconductor device. The processor is further configured to receive a first signature that is signed over the sent random number by the second semiconductor device using a first private key that is stored in the second semiconductor device, among a first private and public key pair, and test the received first signature, using a first public key that is stored in the first semiconductor device, among the first private and public key pair, to determine whether the second semiconductor device is authenticated.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: David Kehlet, Shuanghong Sun, Saikumar Jayaraman, Fariaz Karim