Patents by Inventor Saikumar Jayaraman

Saikumar Jayaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060154080
    Abstract: An underfill material is presented that may be used between an electrical component and a substrate. The underfill material may be a cured epoxy resin composition comprising a liquid or semisolid epoxy resin and a polyfunctional anhydride polymer and/or oligomer curing agent. The use of anhydride polymers and/or oligomers decrease the volatilization of the composition, thereby reducing the porosity of the underfill material. By changing substituents of the anhydride polymer and/or oligomer, the underfill material may be designed to modify viscosity, decrease moisture adsorption, volatilization and modulus, improve mechanical properties, and enhance adhesion.
    Type: Application
    Filed: March 8, 2006
    Publication date: July 13, 2006
    Inventors: Saikumar Jayaraman, Rahul Manepalli
  • Publication number: 20060105497
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 18, 2006
    Inventors: Daewoong Suh, Saikumar Jayaraman
  • Patent number: 7041736
    Abstract: An underfill material is presented that may be used between an electrical component and a substrate. The underfill material may be a cured epoxy resin composition comprising a liquid or semisolid epoxy resin and a polyfunctional anhydride polymer and/or oligomer curing agent. The use of anhydride polymers and/or oligomers decrease the volatilization of the composition, thereby reducing the porosity of the underfill material. By changing substituents of the anhydride polymer and/or oligomer, the underfill material may be designed to modify viscosity, decrease moisture adsorption, volatilization and modulus, improve mechanical properties, and enhance adhesion.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Rahul Manepalli
  • Publication number: 20060073344
    Abstract: An underfill composition includes a thermosetting resin and a thermally cleavable component that releases sulfonic acid upon thermal activation. The underfill composition is applied to flip-chip technology during no-flow underfill mounting of the flip-chip to a mounting substrate. The mounting substrate can be further mounted on a board. A process includes formation of the underfill composition. A method includes assembly of the underfill composition with the flip-chip, and further can include assembly of the mounting substrate to a board. A computing system is also included that uses the underfill composition.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 6, 2006
    Inventor: Saikumar Jayaraman
  • Patent number: 7022790
    Abstract: A copolymer composition including a copolymer having repeat units of structural formula I: where X is selected from —CH2—, —CH2—CH2— and O; m is an integer from 0 to 5; and each occurrence of R1–R4 are independently selected from H; C1 to C25 linear, branched, and cyclic alkyl, aryl, aralkyl, alkaryl, alkenyl and alkynyl that can include one or more hetero atoms selected from O, N, and Si; a group that contains an epoxy functionality; —(CH2)nC(O)OR5; —(CH2)nC(O)OR6; —(CH2)nOR6; —(CH2)nOC(O)R6; —(CH2)nC(O)R6; —(CH2)nOC(O)OR6; and any combination of two of R1, R2, R3, and R4 linked together by a linking group. A portion of the repeat units having structural formula I contain at least one epoxy functional pendant group. The copolymer composition can be included with a material that photonically forms a catalyst in a photodefinable dielectric composition, which can be used to form a photodefinable layer on a substrate.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: April 4, 2006
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventors: Edmund Elce, Takashi Hirano, Jeffrey C. Krotine, Jr., Larry F. Rhodes, Brian L. Goodall, SaiKumar Jayaraman, W. Chris McDougall, Shenliang Sun
  • Publication number: 20060068579
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen Lehman, Mitesh Patel, Tiffany Byrne, Edward Martin, Mohd Erwan Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt Chin
  • Publication number: 20060043614
    Abstract: An apparatus including a first substrate comprising a first set of contact points; a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and a composition disposed between the first substrate and the second substrate including a siloxane-based aromatic diamine.
    Type: Application
    Filed: October 24, 2005
    Publication date: March 2, 2006
    Inventor: Saikumar Jayaraman
  • Patent number: 6981380
    Abstract: Apparatus and methods in accordance with the present invention utilize thermoelectric cooling (TEC) technology to provide enhanced power distribution and/or dissipation from a microelectronic die and/or microelectronic packages. Individual TEC devices are thermally interconnected with the microelectronic die in a number of placement configurations, including between the microelectronic die and the heat sink, on the integrated heat spreader (IHS) inner surface, and on the IHS outer surface. TEC devices comprise p- and n-type semiconducting material created using similar process as the microcircuits. The TEC devices are located in various regions within or on the microelectronic die, including directly below the microcircuits, on the backside of the microelectronic die, and on a separate substrate of microelectronic die material fabricated apart from the microelectronic die and subsequently thermally coupled to the backside of the microelectronic die.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 3, 2006
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, Paul A. Koning, Saikumar Jayaraman, Makarem A. Hussein
  • Publication number: 20050224951
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. An article that exhibits a stress-relief layer with a structure characteristic of the manner of dispensing is also included. A computing system that includes a stress-relief layer with a structure characteristic of the manner of dispensing is also included.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Daewoong Suh, Christos Economopoulos, Saikumar Jayaraman, Mohd Basiron, Sheau Lim, Yoong Chin
  • Publication number: 20050221534
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is mated and the SCC partially embeds the solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes a stress-relief layer and a stress-compensation collar is also included.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Daewoong Suh, Saikumar Jayaraman, Mohd Bin Basiron, Sheau Lim, Yoong P. Chin
  • Publication number: 20050214523
    Abstract: A thermal interface material made with a phase change polymer and a fusible filler material.
    Type: Application
    Filed: May 13, 2005
    Publication date: September 29, 2005
    Inventors: Saikumar Jayaraman, Paul Koning, Ashay Dani
  • Publication number: 20050214977
    Abstract: Apparatus and methods are provided wherein the reflowable electrically conductive interconnect material coupling the interconnects and/or land-side components of a microelectronic package is protected from elevated temperatures, such as those associated with reflow processes and environments which exceed the melting temperature of the interconnect material. One embodiment of the method provides covering the interconnect material about the interconnects and/or land-side components with heat-resistant curable material which protects the interconnect material from the elevated temperature and provides structural support to the interconnects and/or land-side components at the elevated temperature.
    Type: Application
    Filed: May 23, 2005
    Publication date: September 29, 2005
    Inventors: Christopher Rumer, Saikumar Jayaraman
  • Publication number: 20050186502
    Abstract: The present invention relates to a directly photoimageable polymer composition (DPPC) and methods for its use in forming microelectronic and optoelectronic devices. Such DPPC encompasses a polymer having at least one norbornene-type repeat unit having a pendant silyl containing radical and at least one norbornene-type repeat unit having an acrylate containing radical.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 25, 2005
    Inventors: Edmund Elce, Ramakrishna Ravikiran, Larry Rhodes, Robert Shick, Saikumar Jayaraman
  • Patent number: 6926955
    Abstract: According to one aspect of the invention, a structure and method for providing improved thermal conductivity of a thermal interface material (TIM) made of phase changed polymer matrix and a fusible filler material is disclosed. The TIM may also have a non-fusible filler material and a percentage of a non-phase change polymer added to the phase change polymer matrix. The TIM, used to mate and conduct heat between two or more components, can be highly filled systems in a polymeric matrix where the fillers are thermally more conductive than the polymer matrix.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
  • Publication number: 20050159573
    Abstract: The present invention describes a method including: providing a material A, the material A including a siloxane backbone with a hydride functional group; reacting the material A with a material B in the presence of a catalyst to form a material C, the material B including an alkenyl functional group and an aromatic carbonate functional group; heating the material C to form a material D, the material D including a phenol functional group; and reacting the material D with a material E and a material F to form a material G, the material E including a cyanogen halide, the material F including an acid acceptor, the material G including an aromatic cyanate ester functional group. The present invention further describes a die attach adhesive including a three-dimensional network of substituted triazine rings.
    Type: Application
    Filed: December 15, 2004
    Publication date: July 21, 2005
    Inventor: Saikumar Jayaraman
  • Publication number: 20050142345
    Abstract: A mounting substrate includes an at least double-embossed structure on one side for containing metallization traces. The mounting substrate is overlaid with an uncured polymer and it is imprinted and cured by infrared or microwave energy. A second uncured polymer is placed over the cured polymer first film. It is imprinted and also cured under conditions that allow retention of significant features of the cured polymer first film. A chip package is also made of the double-embossed structure. The chip package can include a heat sink. A computing system is also disclosed that includes the double-embossed structure.
    Type: Application
    Filed: December 30, 2003
    Publication date: June 30, 2005
    Inventor: Saikumar Jayaraman
  • Patent number: 6911726
    Abstract: Apparatus and methods are provided wherein the reflowable electrically conductive interconnect material coupling the interconnects and/or land-side components of a microelectronic package is protected from elevated temperatures, such as those associated with reflow processes and environments which exceed the melting temperature of the interconnect material. One embodiment of the method provides covering the interconnect material about the interconnects and/or land-side components with heat-resistant curable material which protects the interconnect material from the elevated temperature and provides structural support to the interconnects and/or land-side components at the elevated temperature.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: June 28, 2005
    Assignee: Intel Corporation
    Inventors: Christopher L. Rumer, Saikumar Jayaraman
  • Patent number: 6903171
    Abstract: Methods for the addition polymerization of cycloolefins using a cationic Group 10 metal complex and a weakly coordinating anion of the formula: [(R?)zM(L?)x(L?)y]b[WCA]d wherein [(R?)zM(L?)x(L?)y] is a cation complex where M represents a Group 10 transition metal; R? represents an anionic hydrocarbyl containing ligand; L? represents a Group 15 neutral electron donor ligand; L? represents a labile neutral electron donor ligand; x is 1 or 2; and y is 0, 1, 2, or 3; and z is 0 or 1, wherein the sum of x, y, and z is 4; and [WCA] represents a weakly coordinating counteranion complex; and b and d are numbers representing the number of times the cation complex and weakly coordinating counteranion complex are taken to balance the electronic charge on the overall catalyst complex.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: June 7, 2005
    Assignee: Promerus, LLC
    Inventors: Larry Funderburk Rhodes, Andrew Bell, Ramakrishna Ravikiran, John C. Fondran, Saikumar Jayaraman, Brian Leslie Goodall, Richard A. Mimna, John-Henry Lipian
  • Publication number: 20050068757
    Abstract: According to one aspect of the present invention, an electronic assembly and a method of forming an electronic assembly are provided. A semiconductor package includes a package substrate with a microelectronic die mounted to a first side and contact formations attached to a second side thereof. A stress compensation layer is formed on the first surface between the contact formations. The semiconductor package is then attached to a circuit board leaving an air space between the stress compensation layer and the circuit board. The stress compensation layer reduces stress on the contact formations and increases solder joint reliability.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Saikumar Jayaraman, Terry Sterrett, Connie Gettinger, Vijay Wakharkar, Agnes Padovani
  • Publication number: 20050019638
    Abstract: A polymer comprising polycyclic repeating units having recurring ion conducting groups and optional crosslinkable groups is disclosed. The present invention provides the capability of tailoring polymers to impart unique properties to membranes fabricated from the polymers. Membranes comprising the polymers and methods for preparing the membranes and their use in ion conducting membranes, particularly in fuel cells, are also provided.
    Type: Application
    Filed: June 4, 2004
    Publication date: January 27, 2005
    Inventors: R. Ravikiran, Xiaoming Wu, Larry Rhodes, Robert Shick, Hiroko Nakano, Hirotaka Nonaka, Huabin Wang, Saikumar Jayaraman, Robert Duff, John-Henry Lipian