Patents by Inventor Sailesh Kumar
Sailesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230350829Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.Type: ApplicationFiled: July 7, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Swadesh Choudhary, Robert G. Blankenship, Siva Prasad Gadey, Sailesh Kumar, Vinit Mathew Abraham, Yen-Cheng Liu
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Publication number: 20230252497Abstract: Systems and methods for measuring impact of online search queries on user actions. The method includes capturing clickstream data entered via a website, the clickstream data including text-based queries associated with web searches, and clustering the queries to generate query clusters. The method also includes assigning each query cluster to an intent such that each assigned intent estimates a desired action behind the queries in the corresponding query cluster. The method further includes mapping each intent assigned to a query cluster to at least one action motivated by the intent. The method also includes computing metrics using the mapping to quantitatively measure the impact of the queries on the mapped actions by tracking performance of the actions within a predefined time period after the queries.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Inventors: Adam Young, Ankush Chopra, Bibhash Chakrabarty, Abhishek Mansing Desai, Sohom Ghosh, Henry Ortiz, Anup Nayak, Sailesh Kumar Sankar Kumar
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Patent number: 11698879Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.Type: GrantFiled: June 27, 2020Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Swadesh Choudhary, Robert G. Blankenship, Siva Prasad Gadey, Sailesh Kumar, Vinit Mathew Abraham, Yen-Cheng Liu
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Publication number: 20230051980Abstract: In an example implementation according to aspects of the present disclosure, a system receives behavioral biometric data associated with a user of a computing device. The system determines whether an identity of the user is authenticated based on a comparison of the received behavior biometric data and historical behavioral biometric data associated with the user of the computing device. In response to determining that the identity of the user is not authenticated based on the comparison of the received behavioral biometric data and the historical behavioral biometric data, the system receives physiological biometric data associated with the user. The system determines whether the identity of the user is authenticated based on a comparison of the received physiological biometric data and historical physiological biometric data associated with the user of the computing device.Type: ApplicationFiled: February 20, 2020Publication date: February 16, 2023Inventors: Sailesh Kumar Tammannagari, Rafael Dal Zotto
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Publication number: 20220012177Abstract: Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA.Type: ApplicationFiled: May 29, 2021Publication date: January 13, 2022Applicant: NETSPEED SYSTEMS, INC.Inventor: Sailesh KUMAR
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Patent number: 11176302Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.Type: GrantFiled: January 25, 2019Date of Patent: November 16, 2021Assignee: NETSPEED SYSTEMS, INC.Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
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Patent number: 11126672Abstract: A method for managing navigation of web content by displaying an indicia on a first content on a screen of the electronic device, the indicia indicating an availability of a second content related to the first content, detecting an input on at least one portion of the first content, and displaying the second content related to the at least one portion of the first content on the screen.Type: GrantFiled: December 11, 2018Date of Patent: September 21, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sailesh Kumar Sathish
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Patent number: 11023377Abstract: Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA.Type: GrantFiled: January 25, 2019Date of Patent: June 1, 2021Assignee: NetSpeed Systems, Inc.Inventor: Sailesh Kumar
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Patent number: 10977311Abstract: A method and a system for dynamically modifying at least one element of a User Interface (UI) of a first electronic device are provided. The method includes collating usage information of at least one data source in the first electronic device, categorizing the collated usage information into one or more knowledge clusters, forming a knowledge graph using the one or more knowledge clusters, and dynamically modifying the at least one element of the UI based on the knowledge graph.Type: GrantFiled: November 6, 2018Date of Patent: April 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sailesh Kumar Sathish, Nirmesh Neema, Bhavani Shankar Yeleswarapu, Ravitheja Tetali, Satnam Singh
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Patent number: 10896476Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.Type: GrantFiled: August 31, 2018Date of Patent: January 19, 2021Assignee: NetSpeed Systems, Inc.Inventors: Nishant Rao, Sailesh Kumar, Pier Giorgio Raponi
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Publication number: 20200327084Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.Type: ApplicationFiled: June 27, 2020Publication date: October 15, 2020Inventors: Swadesh Choudhary, Robert G. Blankenship, Siva Prasad Gadey, Sailesh Kumar, Vinit Mathew Abraham, Yen-Cheng Liu
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Patent number: 10749811Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.Type: GrantFiled: February 23, 2018Date of Patent: August 18, 2020Assignee: NetSpeed Systems, Inc.Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
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Patent number: 10735335Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.Type: GrantFiled: February 23, 2018Date of Patent: August 4, 2020Assignee: NetSpeed Systems, Inc.Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
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Patent number: 10705721Abstract: Embodiments herein provide a method for providing a topic view using an electronic device. The method includes detecting, by a gesture detection unit of the electronic device, a user input on content displayed on a display of the electronic device. Further, the method includes identifying a topic of the content displayed on a display of the electronic device. Further, the method includes determining, by a controller of the electronic device, a degree of similarity between the identified topic and at least one topic related to at least one content displayed on at least one external electronic device corresponding to at least one contact item stored in the electronic device. Further, the method includes displaying a topic view on the display of the electronic device based on the degree of similarity, wherein the topic view comprises at least one indicator indicating the at least one contact item corresponding to at least one topic included in the topic view.Type: GrantFiled: January 23, 2017Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sailesh Kumar Sathish, Vinod Keshav Seetharamu
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Patent number: 10642989Abstract: A method for masking content to be displayed on the electronic device is provided. The method includes receiving, by a processor in the electronic device, the content to be displayed on the electronic device, determining, by the processor, that at least one portion of the content is objectionable content based on a semantic signature of a content filter, and masking, by the processor, the at least one portion of the content displayed on the electronic device based on the detection.Type: GrantFiled: March 6, 2019Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sailesh Kumar Sathish, Vinod Keshav Seetharamu
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Patent number: 10614365Abstract: A platform for managing recommendation models is described. The platform processes and/or facilitates a processing of at least one user identification characteristic associated with at least one device to determine a user identity. The platform further determines at least one communication account active at the at least one device. The platform also causes, at least in part, an association of one or more recommendations models with the user identity, the at least one communication account, the at least one device, or a combination thereof.Type: GrantFiled: November 16, 2015Date of Patent: April 7, 2020Assignee: WSOU INVESTMENTS, LLCInventors: Sailesh Kumar Sathish, Jari P Hamalainen
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Patent number: 10613616Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: February 23, 2018Date of Patent: April 7, 2020Assignee: NetSpeed Systems, Inc.Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 10564704Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: February 23, 2018Date of Patent: February 18, 2020Assignee: NetSpeed Systems, Inc.Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 10564703Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: February 23, 2018Date of Patent: February 18, 2020Assignee: NetSpeed Systems, Inc.Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 10554496Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.Type: GrantFiled: October 28, 2015Date of Patent: February 4, 2020Assignee: NetSpeed SystemsInventors: Eric Norige, Sailesh Kumar