Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Example implementations as described herein are directed to systems and methods for processing a NoC specification for a plurality of performance requirements of a NoC, and generating a plurality of NoCs, each of the plurality of NoCs meeting a first subset of the plurality of performance requirements. For each of the plurality of NoCs, the example implementations involve presenting a difference between an actual performance of the each of the plurality of NoCs and each performance requirement of a second subset of the plurality of performance requirements and one or more costs for each of the plurality of NoCs.

Abstract: Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.

Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.

Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating/constructing NoC based on one or more strategies that are selected by a machine-learning engine (MLE) from a plurality of available strategies based on an input NoC specification. In an aspect, the method can include the steps of processing a Network on Chip (NoC) specification through a process to generate a vector for a plurality of NoC generation strategies, wherein the vector is indicative of which strategies from the plurality of NoC generation strategies are to be used to generate the NoC to meet a quality metric; and generating the NoC by using the strategies from the plurality of NoC generation strategies indicated by the vector as the strategies to be used to generate the NoC, wherein the process is generated through a machine learning process that is trained for the plurality of NoC generation strategies.

Abstract: The present disclosure is directed to machine learning (ML) based network-on-chip (NoC) construction. Example implementations of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is optimized for a desired implementation during construction of a NoC. The ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a ML predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, and quality metrics obtained by implementing a mapping strategy on the NoC to generate an output that provide an indication as to whether the set of strategies results in a good or bad design or whether the provided strategy meets a threshold for the quality metric.

Abstract: The present disclosure is directed to machine learning (ML) based network-on-chip (NoC) construction. Methods, systems, and computer readable mediums of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is actually the most optimal and efficient one or not during construction of a NoC. ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a machine learning algorithm/predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, a quality metrics) obtained by implementing a mapping strategy on the NoC, and one or more performance function (user requirement) to generate an output showing whether the selected strategy for the construction of the NoC yields a good result or a bad result based on learning/training.

Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.

Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: In example implementations of the present disclosure, there is a processing of a specification and/or other parameters to generate a NoC with traffic flows that meet the specification requirements. In example implementations, the specification is processed to determine the characteristics of the NoC to be generated, the characteristics of the traffic flow (e.g. number of hops, bandwidth requirements, type of flow such as request/response, quality of service, traffic type, etc.), flow mapping decision strategy (e.g., limit on number of new virtual channels to be constructed, using of existing VCs, or generation of new, yx/xy mapping, other routing types, traffic flow isolation by layer or by VC depending of the type of traffic, and/or the presence of single or multi-beat traffic, etc.) to be used for how the flows are to be mapped to the network.

Abstract: In example implementations of the present disclosure, there is a processing of a specification and/or other parameters to generate a NoC with traffic flows that meet the specification requirements. In example implementations, the specification is processed to determine the characteristics of the NoC to be generated, the characteristics of the traffic flow (e.g. number of hops, bandwidth requirements, type of flow such as request/response, quality of service, traffic type, etc.), flow mapping decision strategy (e.g., limit on number of new virtual channels to be constructed, using of existing VCs, or generation of new, yx/xy mapping, other routing types, traffic flow isolation by layer or by VC depending of the type of traffic, and/or the presence of single or multi-beat traffic, etc.) to be used for how the flows are to be mapped to the network.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Aspects of the present disclosure are directed to systems, methods and computer readable medium for reducing the number of unique routers/network elements/module instances on a network on chip to get a simplified NoC RTL without effecting the behavior and performance of NoC. According to an example implementation of the present disclosure, plurality of NoC elements of a given NoC can be grouped together to form one or more groups, and one or more superset NoC elements/module instances encompassing capabilities/functionalities of plurality of individual NoC elements of said one or more groups can be determined/created for each of the said one or more groups. In an example implementation, the NoC can be represented by replacing plurality of NoC elements with the created superset NoC elements/module instances, which may reduce the number of unique module instances within an application specific network on chip or system of chip.

Abstract: In example implementations of the present disclosure, there is a processing of a specification and/or other parameters to generate a NoC with traffic flows that meet the specification requirements. In example implementations, the specification is processed to determine the characteristics of the NoC to be generated, the characteristics of the traffic flow (e.g. number of hops, bandwidth requirements, type of flow such as request/response, quality of service, traffic type, etc.), flow mapping decision strategy (e.g., limit on number of new virtual channels to be constructed, using of existing VCs, or generation of new, yx/xy mapping, other routing types, traffic flow isolation by layer or by VC depending of the type of traffic, and/or the presence of single or multi-beat traffic, etc.) to be used for how the flows are to be mapped to the network.

Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.