Patents by Inventor Sakae Kikuchi

Sakae Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8546939
    Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 1, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
  • Patent number: 8295057
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: October 23, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Patent number: 7817437
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: October 19, 2010
    Assignee: Renensas Electronics Corporation
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Publication number: 20100231304
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Application
    Filed: May 25, 2010
    Publication date: September 16, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Publication number: 20090161329
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Application
    Filed: February 27, 2009
    Publication date: June 25, 2009
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Publication number: 20090139615
    Abstract: The present invention provides a leaf spring material superior in mechanical characteristics and a manufacturing method of the leaf spring material capable of reliably achieving the same, utilizing induction hardening. The manufacturing method of the leaf spring material comprises the steps of imparting tensile stress on a first surface along the longitudinal direction of the first surface and compressive stress on a second surface along the longitudinal direction of the second surface of a substantially strip-shaped steel plate, and subjecting the first surface to induction hardening. With this induction hardening, an induction-hardened structure having a higher average hardness than that of a parent material structure in the vicinity of the second surface and comprising martensite and finely and evenly dispersed austenite is imparted on a surface layer in the vicinity of the first surface.
    Type: Application
    Filed: November 26, 2008
    Publication date: June 4, 2009
    Applicants: NHK SPRING CO., LTD, HORIKIRI, INC.
    Inventors: Michihiko Ayada, Yoshiki Ono, Fumio Takahashi, Hironori Ebashi, Sakae Kikuchi
  • Publication number: 20090133785
    Abstract: The present invention provides a leaf spring material superior in mechanical characteristics and a manufacturing method of the leaf spring material capable of reliably achieving the same, utilizing induction hardening. The leaf spring material comprises a substantially strip-shaped steel plate having a first surface and a second surface. The leaf spring material has in the vicinity of the first surface a hardened layer comprising an induction-hardened structure having a higher average hardness than that of the parent material structure in the vicinity of the second surface, and a compressive residual stress layer of a thickness at least not smaller than that of the thickness of the hardened layer in the vicinity of the first surface. Such a characteristic structure is achieved by stress-induced hardening that imparts a predetermined tensile stress or higher.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 28, 2009
    Applicants: NHK SPRING CO., LTD, HORIKIRI, INC.
    Inventors: Michihiko AYADA, Yoshiki ONO, Fumio TAKAHASHI, Hironori EBASHI, Sakae KIKUCHI
  • Patent number: 7525813
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: April 28, 2009
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Patent number: 7453147
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: November 18, 2008
    Assignees: Renesas Technology Corp., Renesas Eastern Semiconductor, Inc.
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Publication number: 20080048777
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Application
    Filed: October 1, 2007
    Publication date: February 28, 2008
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Patent number: 7262480
    Abstract: A high frequency power amplifying device has two amplifying lines. Each amplifying line has a configuration in which a plurality of amplifying stages are connected in cascade having two source voltage terminals, of which one is connected to the first amplifying stage of one amplifying line and to the remaining amplifying stages of the other amplifying line, and the other, to the first amplifying stage of the latter amplifying line and to the remaining amplifying stages of the former amplifying line. An air core coil with a low D.C. resistance, formed by spirally winding a copper wire of about 0.1 mm in diameter, is connected in series between the final amplifying stage of each amplifying line and the source voltage terminal.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: August 28, 2007
    Assignees: Hitachi, Ltd., Eastern Japan Semiconductor Technologies, Akita Electronics Co., Ltd.
    Inventors: Toshihiko Kyogoku, Tadashi Kodu, Kiyoharu Mochiduki, Sakae Kikuchi, Akio Ishidu, Yoshihiko Kobayashi, Masashi Maruyama, Iwamichi Kojiro, Susumu Sato
  • Publication number: 20070190962
    Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).
    Type: Application
    Filed: December 29, 2006
    Publication date: August 16, 2007
    Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
  • Publication number: 20070001300
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Application
    Filed: June 13, 2006
    Publication date: January 4, 2007
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Patent number: 7119004
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 10, 2006
    Assignees: Renesas Technology Corp., Renesas Eastern Japan semiconductor, Inc.
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Patent number: 7068521
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: June 27, 2006
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Publication number: 20060118970
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Application
    Filed: January 6, 2006
    Publication date: June 8, 2006
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Publication number: 20050269590
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Application
    Filed: August 2, 2005
    Publication date: December 8, 2005
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Publication number: 20050248039
    Abstract: A semiconductor device includes: a semiconductor chip having a plurality of pads formed on the main surface thereof; chip components having connection terminals formed on both ends thereof; a module board on which the semiconductor chip and the chip components are mounted; solder connection portions for connecting the chip components to the terminals of the module board and connecting the semiconductor chip to the module board by solder; gold wires for connecting pads of the semiconductor chip to terminals of the module board corresponding thereto; and a sealing section which covers the semiconductor chip, the chip components, solder connection portions and gold wires and is formed of an insulating elastic resin such as silicone resin, wherein the wire height is set to 0.2 mm or less and the wire length is set to 1.5 mm or less so as to prevent the gold wires from being broken.
    Type: Application
    Filed: September 30, 2002
    Publication date: November 10, 2005
    Inventors: Toshihiro Miura, Iwamichi Kohjiro, Sakae Kikuchi
  • Patent number: 6943441
    Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is placed at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 13, 2005
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
  • Publication number: 20040245655
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Application
    Filed: February 13, 2004
    Publication date: December 9, 2004
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi