Patents by Inventor Sakae Kitajo

Sakae Kitajo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6670208
    Abstract: In a method for fabricating an optical circuit, a mirror element with a protection film formed within a die of a semiconductor is connected to a substrate at a predetermined position. The mirror element with the protection film connected to the substrate is peeled from the die of the semiconductor. The protection film is removed to expose a reflection surface of a reflection film of the mirror element.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: December 30, 2003
    Assignee: NEC Corporation
    Inventors: Mikio Oda, Koji Soejima, Sakae Kitajo
  • Patent number: 6611057
    Abstract: A semiconductor device includes two or more semiconductor modules which are stacked up into three-dimensional structure. Each semiconductor module includes a wiring board, one or more IC chips which are mounted on the wiring board, and one or more heat sinks which are attached to the IC chips via a thermal-conductive adhesive and are forcedly cooled by a coolant flowing through channels which are formed therein. The wiring board of each semiconductor module is provided with sockets having I/O pins and concavities. Electrical connection between adjacent semiconductor modules of the semiconductor device is established by inserting the I/O pins of the sockets of one semiconductor module into the concavities of the sockets of the other semiconductor module. The channels in the heat sink are implemented by a plurality of channel grooves which are generated between a plurality of fins which are formed in a cavity inside the heat sink at predetermined intervals.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: August 26, 2003
    Assignee: NEC Corporation
    Inventors: Kazuyuki Mikubo, Sakae Kitajo
  • Publication number: 20030142896
    Abstract: An optical waveguide board is provided which includes a substrate, an optical path changing unit being formed on the substrate used to change a direction of an optical path of incident light from a direction being vertical to a surface of the substrate to a direction being horizontal to the surface of the substrate and to condense a luminous flux and an optical waveguide being formed on the substrate to carry out multi-mode transmission of a luminous flux fed from the optical path changing unit wherein, based on a spread angle of the luminous flux formed by the optical path changing unit, mainly light components to be transmitted in a zero-order mode to a three-order mode only, out of various kinds of modes for the multi-mode transmission, is transmitted through the optical waveguide.
    Type: Application
    Filed: November 1, 2002
    Publication date: July 31, 2003
    Applicant: NEC CORPORATION
    Inventors: Hideo Kikuchi, Junichi Sasaki, Seiji Suda, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada
  • Publication number: 20030128907
    Abstract: After an optical waveguide substrate including a supporting substrate is adhered to an electric wiring board, the supporting substrate alone is dissolved using an organic solvent for removal. Alternatively, the supporting substrate alone is melted through a thermal treatment for removal. Further, a core layer of an optical waveguide is formed on the substrate using a photosensitive resin having a thermal expansion coefficient substantially identical to that of the supporting substrate.
    Type: Application
    Filed: November 26, 2002
    Publication date: July 10, 2003
    Applicant: NEC TOPPAN CIRCUIT SOLUTION, INC.
    Inventors: Hideo Kikuchi, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada
  • Publication number: 20030116347
    Abstract: An electronic component is described, which contains a printed circuit board having electrodes for connection and a semiconductor chip having electrodes for connection which is mounted on said circuit board with their electrodes facing those of the circuit board, the gap between the circuit board and the semiconductor chip being filled with a sealing resin layer, wherein the sealing resin layer is formed of a liquid epoxy resin composition containing (A) a liquid epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) an N,N,N′,N′-tetrasubstituted fluorine-containing aromatic diamine derivative.
    Type: Application
    Filed: September 19, 2002
    Publication date: June 26, 2003
    Applicants: NITTO DENKO CORPORATION, NEC CORPORATION
    Inventors: Masahiro Kubo, Ichiro Hazeyama, Sakae Kitajo, Koji Matsui, Kazumasa Igarashi
  • Publication number: 20030117690
    Abstract: An optical path control apparatus includes a first substrate. A second substrate is movably provided for the first substrate. A mirror section is provided on the second substrate. A driving section moves the second substrate such that a first optical path of input light to the mirror section is optically connected to one of a plurality of second optical paths.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Mikio Oda, Mitsuru Yamamoto, Hikaru Kouta, Yasuhiro Sasaki, Sakae Kitajo, Yuzo Shimada
  • Publication number: 20030117614
    Abstract: There is disclosed a method of inspecting an optical waveguide substrate for optical conduction at an increased inspecting rate and also inspecting an optical waveguid—e substrate for cross-talk. According to the disclosed method, a laser beam is applied from a laser beam scanning optical system to one end face of an optical waveguide of an optical waveguide substrate which is an object to be inspected, and the laser beam emitted from the other end of the optical waveguide is detected by a CCD camera, which output detected result data. A light spot position confirming device compares the detected result data with stored data.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 26, 2003
    Applicant: NEC Toppan Circuit Solutions, Inc.
    Inventors: Hideo Kikuchi, Mikio Oda, Hikaru Kouta, Sakae Kitajo, Yuzo Shimada, Yoshio Matsumoto, Shinichi Tamabayashi
  • Publication number: 20030053765
    Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.
    Type: Application
    Filed: September 26, 2002
    Publication date: March 20, 2003
    Applicant: NEC CORPORATION
    Inventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
  • Publication number: 20020185718
    Abstract: A semiconductor package comprising an LSI chip, a chip bump, an interposer, and a BGA bump is mounted at a predetermined position of a printed wiring board having a core layer. A heat sink for dissipating heat generated from the LSI chip is installed within the core layer. Further, heat radiating vias for conveying heat generated from the LSI chip to the heat sink are provided within the printed wiring board so that the BGA bump in the LSI chip is thermally liked with the heat sink. The heat generated from the LSI chip is mainly dissipated through a route of chip bump→interposer→BGA bump→heat radiating via→heat sink. By virtue of the above construction, the semiconductor device packaging structure can reduce the packaging volume of the heat sink while providing satisfactory cooling capacity and, at the same time, can minimize the length of signal wiring between LSI chips.
    Type: Application
    Filed: March 4, 2002
    Publication date: December 12, 2002
    Inventors: Kazuyuki Mikubo, Sakae Kitajo, Yuzo Shimada
  • Patent number: 6477284
    Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: November 5, 2002
    Assignee: NEC Corporation
    Inventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
  • Publication number: 20020135064
    Abstract: Conductive balls are transferred from a pallet onto an array of conductive pads on a semiconductor chip by means of a transfer apparatus; the transfer apparatus includes a pallet formed with an array of recesses same in pattern as the array of conductive pads, a movable head formed with an array of vacuum holes and a driving mechanism for moving the head from an idle position onto the pallet and from the pallet to the semiconductor chip; when the head is moved to the pallet, the vacuum holes are connected to the recesses so as to confine the conductive balls in the narrow spaces; the vacuum is developed; then the conductive balls are traveled through the closed spaces to the vacuum holes; even if the conductive balls have been charged, the conductive balls are never attracted to the adjacent balls, and are surely captured by the vacuum holes.
    Type: Application
    Filed: March 25, 2002
    Publication date: September 26, 2002
    Applicant: NEC Corporation
    Inventors: Ichiro Hazeyama, Sakae Kitajo, Yuzo Shimada, Akeo Katahira, Jun Ishida, Masaru Terashima, Kazuhiko Futakami
  • Patent number: 6438504
    Abstract: The thermal resistance of an entire semiconductor package with a semiconductor chip and radiation fins is calculated based on thermal resistance of resin between the semiconductor chip and case, thermal resistance of the radiation fins, and thermal resistance of three heat radiation paths in the semiconductor package. One of said three heat radiation paths is passing through the bottom surface of the case. The other of said three radiation paths is passing through the leadframe. The other of three radiation paths is passing through sides of the case other than the leadframe.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: August 20, 2002
    Assignee: NEC Corporation
    Inventors: Kazuyuki Mikubo, Sakae Kitajo
  • Patent number: 6430327
    Abstract: After an optical element 6, and more preferably both an optical element 6 and an electrical element 7, are mounted on a substrate 1, an upper clad 5 of optical waveguide is formed, covering these elements, and thereby a structure of hermetic seal is achieved through the use of the upper clad 5.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: August 6, 2002
    Assignee: NEC Corporation
    Inventors: Yoshinobu Kaneyama, Masataka Ito, Masahiko Fujiwara, Sakae Kitajo, Mikio Oda, Yuzo Shimada
  • Publication number: 20020053726
    Abstract: A semiconductor device includes two or more semiconductor modules which are stacked up into three-dimensional structure. Each semiconductor module includes a wiring board, one or more IC chips which are mounted on the wiring board, and one or more heat sinks which are attached to the IC chips via a thermal-conductive adhesive and are forcedly cooled by a coolant flowing through channels which are formed therein. The wiring board of each semiconductor module is provided with sockets having I/O pins and concavities. Electrical connection between adjacent semiconductor modules of the semiconductor device is established by inserting the I/O pins of the sockets of one semiconductor module into the concavities of the sockets of the other semiconductor module. The channels in the heat sink are implemented by a plurality of channel grooves which are generated between a plurality of fins which are formed in a cavity inside the heat sink at predetermined intervals.
    Type: Application
    Filed: November 8, 2001
    Publication date: May 9, 2002
    Inventors: Kazuyuki Mikubo, Sakae Kitajo
  • Publication number: 20020001870
    Abstract: In a method for fabricating an optical circuit, a mirror element with a protection film formed within a die of a semiconductor is connected to a substrate at a predetermined position. The mirror element with the protection film connected to the substrate is peeled from the die of the semiconductor. The protection film is removed to expose a reflection surface of a reflection film of the mirror element.
    Type: Application
    Filed: February 28, 2001
    Publication date: January 3, 2002
    Inventors: Mikio Oda, Koji Soejima, Sakae Kitajo
  • Publication number: 20010048708
    Abstract: The thermal resistance of an entire semiconductor package with a semiconductor chip and radiation fins is calculated based on thermal resistance of resin between the semiconductor chip and case, thermal resistance of the radiation fins, and thermal resistance of three heat radiation paths in the semiconductor package. One of said three heat radiation paths is passing through the bottom surface of the case. The other of said three radiation paths is passing through the leadframe. The other of three radiation paths is passing through sides of the case other than the leadframe.
    Type: Application
    Filed: March 28, 2001
    Publication date: December 6, 2001
    Inventors: Kazuyuki Mikubo, Sakae Kitajo
  • Patent number: 6238086
    Abstract: The thermal resistance of an entire semiconductor package with a semiconductor chip and radiation fins is calculated based on thermal resistance of resin between the semiconductor chip and case, thermal resistance of the radiation fins, and thermal resistance of three heat radiation paths in the semiconductor package. One of said three heat radiation paths is passing through the bottom surface of the case. The other of said three radiation paths is passing through the leadframe. The other of three radiation paths is passing through sides of the case other than the leadframe.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: May 29, 2001
    Assignee: NEC Corporation
    Inventors: Kazuyuki Mikubo, Sakae Kitajo
  • Patent number: 5838066
    Abstract: To provide a semiconductor device heatsink that is mounted to a semiconductor device and that improves the cooling efficiency, a semiconductor device heatsink has a configuration in that the heatsink has a group of fins 1 and an air-blowing fan, the fins being formed by a large number of plates or pins on top of a base and the air-blowing fan comprising a fan rotating mechanism and a centrifugal fan 2, covers 3 and 4 being provided on the group of fins and the centrifugal fan and further an air intake aperture being provided on the centrifugal fan cover, in the direction of rotation. A centrifugal fan, rather than an axial fan as used in the past, is used, covers are provided on the heatsink and on the fan, so that air does not leak to the outside, and an air intake aperture is provided on the side of the fan cover. By doing this, heat radiating performance is improved, while making it possible to achieve a compact heatsink, which contributes to the compactness of the electronic equipment in which it is used.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: November 17, 1998
    Assignee: NEC Corporation
    Inventor: Sakae Kitajo
  • Patent number: 5241452
    Abstract: Disclosed is a heat-sink equipped package in which a heat sink has a plurality of flat plates arranged in a row, and both end plates have a rectangular shape, while those plates located between the end plates are each an inverted trapezoid having the bottom side shorter than the top side. This structure of the heat sink allows air to easily flow through the bottom portions of the plates. The cooling air therefore leaks outside less, and passes through the spacings between the plates, increasing the cooling performance of the heat sink and improving the cooling efficiency of the package.
    Type: Grant
    Filed: September 10, 1992
    Date of Patent: August 31, 1993
    Assignee: NEC Corporation
    Inventor: Sakae Kitajo