Patents by Inventor Sakae Koyata

Sakae Koyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8759229
    Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 24, 2014
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
  • Patent number: 8466071
    Abstract: An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot is spun, and a front surface of the wafer is etched with an etching solution supplied thereto. In the method, a plurality of supply nozzles are disposed above and opposite to the front surface of the wafer at different portions in the radial direction of the wafer, respectively; and then one or more conditions selected from the group consisting of temperatures, kinds, and supply flow rates of etching solutions from the plurality of supply nozzles are changed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 18, 2013
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Patent number: 8066896
    Abstract: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating device, and a second fluid-aspirating device. The etching fluid supplied on the wafer is spread by a rotation of the wafer. The etching fluid is scattered by a centrifugal force, or flows down over an edge portion of the wafer and is blown-off by the gas injected from the gas injection unit, and is aspirated by the first fluid-aspirating device or the second fluid-aspirating device.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: November 29, 2011
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Patent number: 7955982
    Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 7, 2011
    Assignee: Sumco Corporation
    Inventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Patent number: 7906438
    Abstract: An object of the present invention is to provide a single wafer etching apparatus realizing a high flatness of wafers and an increase in productivity thereof. In the single wafer etching apparatus, a single thin disk-like wafer sliced from a silicon single crystal ingot is mounted on a wafer chuck and spun thereon, and an overall front surface of the wafer is etched with an etching solution supplied thereto by centrifugal force generated by spinning the wafer 11. The singe wafer etching apparatus includes a plurality of supply nozzles 26, 27 capable of discharging the etching solution 14 from discharge openings 26a, 27a onto the front surface of the wafer 11, nozzle-moving devices each capable of independently moving the plurality of supply nozzles 28, 29, and an etching solution supplying device 30 for supplying the etching solution 14 to each of the plurality of supply nozzles and discharging the etching solution 14 from each of the discharge openings to the front surface of the wafer 11.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: March 15, 2011
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Patent number: 7851375
    Abstract: An alkali etchant for controlling surface roughness of a semiconductor wafer, which is a sodium hydroxide solution or a potassium hydroxide solution having a weight concentration of 55 wt % to 70 wt %.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: December 14, 2010
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi
  • Publication number: 20100151597
    Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.
    Type: Application
    Filed: January 17, 2007
    Publication date: June 17, 2010
    Applicant: SUMCO CORPORATION
    Inventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Patent number: 7717768
    Abstract: This wafer polishing apparatus includes: a polishing plate having a polishing pad; a carrier plate which is placed facing the polishing pad and which slides and presses wafers against the polishing pad, while rotating in a state of holding the wafers; and an abrasive slurry supply device, wherein the abrasive slurry supply device is able to supply different abrasive slurries, each of the abrasive slurries contains abrasives of which the average grain size is different from those contained in the other abrasive slurries. This method for polishing wafers includes: while supplying an abrasive slurry to a surface of a polishing pad, sliding and pressing wafers against the polishing pad, wherein different abrasive slurries are supplied to the surface of the polishing pad, and each of the abrasive slurries contains abrasives of which the average grain size is different from those contained in the other abrasive slurries.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 18, 2010
    Assignee: Sumco Corporation
    Inventors: Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Publication number: 20100021688
    Abstract: A wafer manufacturing method includes after flattening both upper and lower surfaces of a wafer sliced from a single crystal ingot, processing the wafer having damage on both surfaces caused by the flattening, so as to obtain desired damage at least on the lower surface of the wafer, the desired damage having a damage depth ranging from 5 nm-10 ?m; forming a polysilicon layer at least on the lower surface of the wafer while the damage on the lower surface of the wafer remains; single-wafer etching the upper surface of the wafer; and final polishing the upper surface of the wafer to have a mirrored surface, after the single-wafer etching.
    Type: Application
    Filed: July 21, 2009
    Publication date: January 28, 2010
    Applicant: SUMCO CORPORATION
    Inventors: Takeo KATOH, Tomohiro HASHII, Katsuhiko MURAYAMA, Sakae KOYATA, Kazushige TAKAISHI
  • Patent number: 7648890
    Abstract: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching solution over all the surface of the wafer; and a grinding step of grinding the surface of the wafer, in this order, wherein the etching solution used in the single-wafer etching step is an aqueous acid solution which contains hydrogen fluoride, nitric acid, and phosphoric acid in an amount such that the content of which by weight % at a mixing rate of fluoric acid:nitric acid:phosphoric acid is 0.5 to 40%:5 to 50%:5 to 70%, respectively.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: January 19, 2010
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Patent number: 7645702
    Abstract: The manufacturing method of the present invention provides a silicon wafer, both sides of the wafer having a highly accurate flatness and small surface roughness, which is a single surface mirror-polished wafer with the front and rear surfaces of the wafer identifiable by visual observation, and excellent in flatness when held by a stepper chuck and the like. The manufacturing method of the present invention includes an etching process, a lapping process, and a double surface polishing process to simultaneously polish the front and rear surfaces of a wafer after the etching process. The polishing removal depth (A) of the wafer front surface is 5 to 10 ?m in the double surface simultaneous polishing process, and the polishing removal depth (B) in the rear surface is 2 to 6 ?m, and a difference between the polishing removal depth A and the polishing removal depth B is 3 to 4 ?m.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: January 12, 2010
    Assignee: SUMCO Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi
  • Publication number: 20090297755
    Abstract: A semiconductor wafer has a diameter of 450 mm and a thickness of at least 725 ?m and no greater than 900 ?m.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 3, 2009
    Applicants: SUMCO CORPORATION, SUMCO TECHXIV CORPORATION
    Inventors: Sakae KOYATA, Tomohiro HASHII, Yasunori YAMADA, Satoshi YUKIWAKI, Shinji SAKAMOTO, Tomoko OHMACHI
  • Patent number: 7601642
    Abstract: The inventive method for processing a silicon wafer is a method comprising step 11 in which a single crystal ingot is sliced into thin disc-like wafers; step 13 in which the surface of each wafer is lapped to be planar; step 14 in which the wafer is subjected to alkaline cleaning to be removed of contaminants resulting from preceding machining; and step 16 in which the wafer is alternately transferred between two groups of etching tanks one of which contain acidic etching solutions and the other alkaline etching solutions, wherein an additional step 12 is introduced between step 11 and step 13 in which a wafer is immersed in an acidic solution containing hydrofluoric acid (HF) and nitric acid (HNO3) at a volume ratio of ? to ½ (HF/HNO3) so that degraded superficial layers occurring on the front and rear surfaces of the wafer as a result of machining can be removed and the edge surface of the wafer can be beveled.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: October 13, 2009
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi
  • Patent number: 7601644
    Abstract: This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning and the entire wafer surface is etched to control the surface roughness Ra to 0.20 ?m or less, and a double-sided simultaneous polishing step, in which the front surface and the rear surface of the acid etched wafer are polished simultaneously. The process may comprise a single-sided polishing step, in which the top and bottom of the acid etched wafer are polished in turn, instead of the double-sided simultaneously polishing step.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: October 13, 2009
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20090181546
    Abstract: A single-wafer etching apparatus according to the present invention supplies an etchant to an upper surface of a wafer while rotating the wafer, thereby etching the upper surface of the wafer. Further, wafer elevating means moves up and down the wafer, and a lower surface blow mechanism which blows off the etchant flowing down on an edge surface of the wafer toward a radially outer side of the wafer by injection of a gas is fixed and provided without rotating together with the wafer. Furthermore, gap adjusting means controls the wafer elevating means based on detection outputs from gap detecting means for detecting a gap between the wafer and the lower surface blow mechanism, thereby adjusting the gap. The apparatus according to the present invention uniformly etches the edge portion without collapsing a chamfered shape of the edge portion of the wafer, and prevents a glitter from being produced on the edge surface of the wafer.
    Type: Application
    Filed: March 31, 2008
    Publication date: July 16, 2009
    Inventors: Takeo KATOH, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Publication number: 20090117749
    Abstract: Local shape collapse of a wafer end portion is suppressed to the minimum level, and a wafer front surface as well as a wafer end portion is uniformly etched while preventing an etchant from flowing to a wafer rear surface. There is provided an etching method of a single wafer which supplies an etchant onto a wafer front surface in a state where a single wafer having flattened front and rear surfaces is held, and etches the wafer front surface and a front surface side end portion by using a centrifugal force generated by horizontally rotating the wafer. According to this method, the etchant is intermittently supplied onto the front surface of the wafer in twice or more, supply of the etchant is stopped after the etchant for one process is supplied, and the etchant for the next process is supplied after the supplied etchant flows off from the end portion of the wafer.
    Type: Application
    Filed: October 28, 2008
    Publication date: May 7, 2009
    Inventors: Sakae KOYATA, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20090053894
    Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.
    Type: Application
    Filed: January 24, 2007
    Publication date: February 26, 2009
    Inventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
  • Publication number: 20090042390
    Abstract: It is possible to reduce workloads of a both-side simultaneous polishing process or a single-side polishing process, and to achieve both of the maintenance of the wafer flatness and the reduction in wafer front side roughness upon completing a flattening process. A method for manufacturing silicon wafers according to the present invention includes a flattening process 13 of grinding or lapping front and back sides of a thin disc-shaped silicon wafer obtained by slicing a silicon single crystal ingot, an etching process of immersing the silicon wafer in an etchant for controlling a silicon wafer surface shape in which a fluorochemical surfactant is uniformly mixed in an alkaline aqueous solution to etch the front and back sides of the silicon wafer, and a both-side simultaneous polishing process 16 of simultaneously polishing the front and back sides of the etched silicon wafer or a single-side polishing process of polishing the front and back sides of the etched wafer for every side, in this order.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Inventors: Sakae Koyata, Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi
  • Patent number: 7488400
    Abstract: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating device, and a second fluid-aspirating device. The etching fluid supplied on the wafer is spread by a rotation of the wafer. The etching fluid is scattered by a centrifugal force, or flows down over an edge portion of the wafer and is blown-off by the gas injected from the gas injection unit, and is aspirated by the first fluid-aspirating device or the second fluid-aspirating device.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: February 10, 2009
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20090004876
    Abstract: An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot is spun, and a front surface of the wafer is etched with an etching solution supplied thereto. In the method, a plurality of supply nozzles are disposed above and opposite to the front surface of the wafer at different portions in the radial direction of the wafer, respectively; and then one or more conditions selected from the group consisting of temperatures, kinds, and supply flow rates of etching solutions from the plurality of supply nozzles are changed.
    Type: Application
    Filed: January 24, 2007
    Publication date: January 1, 2009
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh