Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.

Abstract: An on-chip microwave filter circuit includes a substrate formed of a first material that exhibits at least a threshold level of thermal conductivity, wherein the threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum computing circuit operates. The filter circuit further includes a dispersive component configured to filter a plurality of frequencies in an input signal, the dispersive component including a first transmission line disposed on the substrate, the first transmission line being formed of a second material that exhibits at least a second threshold level of thermal conductivity, wherein the second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum computing circuit operates. The dispersive component further includes a second transmission line disposed on the substrate, the second transmission line being formed of the second material.

Abstract: A stripline that is usable in a quantum application (q-stripline) includes a first polyimide film and a second polyimide film. The q-stripline further includes a first center conductor and a second center conductor formed between the first polyimide film and the second polyimide film. The q-stripline has a first pin configured through the second polyimide film to make electrical and thermal contact with the first center conductor.

Abstract: A stripline that is usable in a quantum application (q-stripline) includes a first polyimide film and a second polyimide film. The q-stripline further includes a first center conductor and a second center conductor formed between the first polyimide film and the second polyimide film. The q-stripline has a first pin configured through a first recess in the second polyimide film to make electrical and thermal contact with the first center conductor.

Abstract: A microstrip that is usable in a quantum application (q-microstrip) includes a ground plane, a polyimide film disposed over the ground plane at a first surface of the polyimide film, and a conductor formed on a second side of the polyimide film such that the first surface is substantially opposite to the second surface. A material of the conductor provides greater than a threshold thermal conductivity (TH) with a structure of a dilution fridge stage (stage).

Abstract: A quantum computer includes a refrigeration system under vacuum including a containment vessel, a qubit chip contained within a refrigerated vacuum environment defined by the containment vessel. The quantum computer further includes a plurality of interior electromagnetic waveguides and a plurality of exterior electromagnetic waveguides. The quantum computer further includes a hermetic connector assembly operatively connecting the interior electromagnetic waveguides to the exterior electromagnetic waveguides while maintaining the refrigerated vacuum environment. The hermetic connector assembly includes an exterior multi-waveguide connector, an interior multi-waveguide connector, and a dielectric plate arranged between and hermetically sealed with the exterior multi-waveguide connector and the interior multi-waveguide connector. The dielectric plate permits electromagnetic energy when carried by the interior and exterior pluralities of electromagnetic waveguides to pass therethrough.

Abstract: A microstrip that is usable in a quantum application (q-microstrip) includes a ground plane, a polyimide film disposed over the ground plane at a first surface of the polyimide film, and a conductor formed on a second side of the polyimide film such that the first surface is substantially opposite to the second surface. A material of the conductor provides greater than a threshold thermal conductivity (TH) with a structure of a dilution fridge stage (stage). The stage is maintained at a cryogenic temperature, and the material of the conductor bonds at the cryogenic temperature with a second material of a part of a connector of a microwave line.

Abstract: Verifying a quantum circuit layout design is provided. A qubit layout is received as input. The qubit layout is generated from a qubit schematic. The qubit schematic includes a plurality of qubits, a plurality of coupling buses, a plurality of readout buses, and a plurality of readout ports. Design rules checking is performed on the qubit layout input, using a predefined set of design rule. The bus style/frequency and qubit information are extracted from the qubit layout input. A new qubit schematic is generated from the extracted bus style/frequency and qubit information. The qubit layout is verified based on the new qubit schematic being the same as the qubit schematic.

Abstract: An on-chip microwave filter circuit includes a substrate formed of a first material that exhibits at least a threshold level of thermal conductivity, wherein the threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum computing circuit operates. The filter circuit further includes a dispersive component configured to filter a plurality of frequencies in an input signal, the dispersive component including a first transmission line disposed on the substrate, the first transmission line being formed of a second material that exhibits at least a second threshold level of thermal conductivity, wherein the second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum computing circuit operates. The dispersive component further includes a second transmission line disposed on the substrate, the second transmission line being formed of the second material.

Abstract: Generating a layout for a multi-qubit chip is provided. A schematic is received as input. The schematic input includes a plurality of qubits, a plurality of coupling busses, a bus design parameter specifying a bus frequency, a plurality of readout busses, and a plurality of readout ports. A qubit design is selected from a qubit library, based on the qubit style in the schematic input. A bus style is selected from a bus information library, based on the bus style in the schematic input. A qubit layout is automatically generated by assembling the selected bus style/, selected qubit design, the plurality of readout busses and the plurality of readout ports.

Abstract: A microstrip that is usable in a quantum application (q-microstrip) includes a ground plane, a polyimide film disposed over the ground plane at a first surface of the polyimide film, and a conductor formed on a second side of the polyimide film such that the first surface is substantially opposite to the second surface. A material of the conductor provides greater than a threshold thermal conductivity (Tx) with a structure of a dilution fridge stage (stage). The stage is maintained at a cryogenic temperature, and the material of the conductor bonds at the cryogenic temperature with a second material of a part of a connector of a microwave line.

Abstract: A stripline that is usable in a quantum application (q-stripline) includes a first polyimide film and a second polyimide film. The q-stripline further includes a first center conductor and a second center conductor formed between the first polyimide film and the second polyimide film. The q-stripline has a first pin configured through a first recess in the second polyimide film to make electrical and thermal contact with the first center conductor.

Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.

Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.

Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.

Abstract: Generating a layout for a multi-qubit chip is provided. A schematic is received as input. The schematic input includes a plurality of qubits, a plurality of coupling busses, a bus design parameter specifying a bus frequency, a plurality of readout busses, and a plurality of readout ports. A qubit design is selected from a qubit library, based on the qubit style in the schematic input. A bus style is selected from a bus information library, based on the bus style in the schematic input. A qubit layout is automatically generated by assembling the selected bus style/, selected qubit design, the plurality of readout busses and the plurality of readout ports.

Abstract: Verifying a quantum circuit layout design is provided. A qubit layout is received as input. The qubit layout is generated from a qubit schematic. The qubit schematic includes a plurality of qubits, a plurality of coupling buses, a plurality of readout buses, and a plurality of readout ports. Design rules checking is performed on the qubit layout input, using a predefined set of design rule. The bus style/frequency and qubit information are extracted from the qubit layout input. A new qubit schematic is generated from the extracted bus style/frequency and qubit information. The qubit layout is verified based on the new qubit schematic being the same as the qubit schematic.

Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.