Patents by Inventor Salvatore Frank Pavone

Salvatore Frank Pavone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100678
    Abstract: In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 24, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Daniel Manack, Salvatore Frank Pavone, Maricel Fabia EscaƱo, Rafael Jose Lizares Guevara
  • Patent number: 12068221
    Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Publication number: 20240194574
    Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.
    Type: Application
    Filed: February 23, 2024
    Publication date: June 13, 2024
    Inventors: Benjamin Stassen Cook, Yogesh Kumar Ramadass, Salvatore Frank Pavone, Mahmud Halim Chowdhury
  • Patent number: 11984418
    Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 14, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Nazila Dadvand, Salvatore Frank Pavone, Patrick Francis Thompson
  • Publication number: 20240153888
    Abstract: A method includes plating a first conductive layer on a second conductive layer, the second conductive layer coupled to a device side of a semiconductor die; using a vapor deposition technique to deposit a silicon nitride layer on the first conductive layer at a pressure lower than 100 Torr; and plating a second conductive layer abutting the first conductive layer, the second conductive layer configured to receive a solder ball.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: Jonathan Andrew MONTOYA, Salvatore Franks PAVONE
  • Publication number: 20240153903
    Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: Katleen Fajardo Timbol, Salvatore Frank Pavone, Rafael Jose Lizares Guevara
  • Patent number: 11948871
    Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: April 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Yogesh Kumar Ramadass, Salvatore Frank Pavone, Mahmud Halim Chowdhury
  • Patent number: 11876065
    Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Katleen Fajardo Timbol, Salvatore Frank Pavone, Rafael Jose Lizares Guevara
  • Patent number: 11876056
    Abstract: In some examples, a semiconductor package includes a semiconductor die; a passivation layer abutting a device side of the semiconductor die; a first conductive layer abutting the device side of the semiconductor die; a second conductive layer abutting the first conductive layer and the passivation layer; a silicon nitride layer abutting the second conductive layer, the silicon nitride layer having a thickness ranging from 300 Angstroms to 3000 Angstroms; and a third conductive layer coupled to the second conductive layer at a gap in the silicon nitride layer, the third conductive layer configured to receive a solder ball.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan Andrew Montoya, Salvatore Franks Pavone
  • Patent number: 11855024
    Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 26, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Qiao Chen, Vivek Swaminathan Sridharan, Christopher Daniel Manack, Patrick Francis Thompson, Jonathan Andrew Montoya, Salvatore Frank Pavone
  • Publication number: 20230104156
    Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 6, 2023
    Inventors: Katleen Fajardo Timbol, Salvatore Frank Pavone, Rafael Jose Lizares Guevara
  • Publication number: 20230065075
    Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Qiao CHEN, Vivek Swaminathan SRIDHARAN, Christopher Daniel MANACK, Patrick Francis THOMPSON, Jonathan Andrew MONTOYA, Salvatore Frank PAVONE
  • Patent number: 11594504
    Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Patent number: 11587858
    Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: February 21, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Publication number: 20230005807
    Abstract: A device includes a semiconductor die including a via, a layer of titanium tungsten (TiW) in contact with the via, and a copper pillar including a top portion and a bottom portion. The bottom portion is in contact with the layer of TiW. The copper pillar includes interdiffused zinc within the bottom portion.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Keith Edward Johnson, Christopher Daniel Manack, Salvatore Frank Pavone
  • Publication number: 20220415762
    Abstract: A semiconductor package includes a semiconductor die including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the semiconductor package, a sensor on a surface of the semiconductor die, laser shielding forming a perimeter around the sensor on the surface of the semiconductor die, and a mold compound surrounding the semiconductor die except for an area inside the perimeter on the surface of the semiconductor die such that the sensor is exposed to an external environment.
    Type: Application
    Filed: June 27, 2021
    Publication date: December 29, 2022
    Inventors: Christopher Daniel Manack, Jonathan Andrew Montoya, Steven Alfred Kummerl, Salvatore Frank Pavone
  • Publication number: 20220384375
    Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Vivek Swaminathan Sridharan, Christopher Daniel Manack, Nazila Dadvand, Salvatore Frank Pavone, Patrick Francis Thompson
  • Publication number: 20220375836
    Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 24, 2022
    Inventors: Benjamin Stassen Cook, Yogesh Kumar Ramadass, Salvatore Frank Pavone, Mahmud Halim Chowdhury
  • Publication number: 20220352098
    Abstract: In some examples, a semiconductor package includes a semiconductor die; a passivation layer abutting a device side of the semiconductor die; a first conductive layer abutting the device side of the semiconductor die; a second conductive layer abutting the first conductive layer and the passivation layer; a silicon nitride layer abutting the second conductive layer, the silicon nitride layer having a thickness ranging from 300 Angstroms to 3000 Angstroms; and a third conductive layer coupled to the second conductive layer at a gap in the silicon nitride layer, the third conductive layer configured to receive a solder ball.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: Jonathan Andrew MONTOYA, Salvatore Franks PAVONE
  • Patent number: 11443996
    Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Keith Edward Johnson, Christopher Daniel Manack, Salvatore Frank Pavone