Patents by Inventor Salvatore Pisasale
Salvatore Pisasale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120159095Abstract: An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal.Type: ApplicationFiled: December 13, 2011Publication date: June 21, 2012Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Daniele Mangano, Salvatore Pisasale, Ignazio Antonino Urzi'
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Publication number: 20110131189Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.Type: ApplicationFiled: November 22, 2010Publication date: June 2, 2011Applicant: STMicroelectronics S.r.I.Inventors: Daniele MANGANO, Giovanni Strano, Salvatore Pisasale
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Publication number: 20110022745Abstract: An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data.Type: ApplicationFiled: July 9, 2010Publication date: January 27, 2011Applicant: STMicroelectronics S.r.I.Inventors: Francesco Giotta, Salvatore Pisasale, Giuseppe Falconeri
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Publication number: 20100322625Abstract: A transmitter for generating, starting from a data-packet traffic at input, flows of information to be conveyed via optical signals with different wavelengths towards a plurality of targets in a communications network, the transmitter including: a destination decoder to identify, for each packet in the input packet traffic, a respective destination target in the plurality of targets; a plurality of emitter modules operating at different wavelengths for converting the electrical signals into optical signals; and a de-multiplexer, which is controlled by the destination decoder and is able to drive the emitter modules by sending selectively to each emitter module the electrical signals corresponding to a given packet of the input packet traffic according to the respective destination target identified by the destination decoder. A serialization module is set upstream of the de-multiplexer for converting the packet traffic into a serial flow of bits.Type: ApplicationFiled: May 28, 2010Publication date: December 23, 2010Applicant: STMICROELECTRONICS S.R.L.Inventors: Alberto Scandurra, Mirko Dondini, Salvatore Pisasale, Letizia Fragomeni
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Publication number: 20100322638Abstract: An on-chip receiver for flows of information conveyed to a target via optical signals with different wavelengths includes a plurality of photo-detector modules, each sensitive to a different wavelength, for converting a respective optical signal at input into an electrical signal, a plurality of de-serialization circuits acting on the electrical signals for converting into packet traffic the flows of information received via the photo-detector modules, and an arbitration node acting on the packet traffic to enable a single packet at a time to achieve the target.Type: ApplicationFiled: May 28, 2010Publication date: December 23, 2010Applicant: STMicroelectronics S.r.I.Inventors: Alberto Scandurra, Giuseppe Guarnaccia, Salvatore Pisasale, Fabio Zito
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Patent number: 7676685Abstract: A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies. The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, a maximum rate of the data transfer, with the rate being a function of all the possible input and output delays supported by the SoC. This is dependent on the parameters of the SoC. There is also a phase for programming a generic frequency converter between the first and second integrated processors for the data transfer, and a phase for scheduling the data transfer between the semi-synchronous clock domains.Type: GrantFiled: May 31, 2006Date of Patent: March 9, 2010Assignee: STMicroelectronics S.R.L.Inventors: Marco Castano, Salvatore Pisasale, Carmine Ciofi, Francesco Giotta
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Publication number: 20060271806Abstract: A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, a maximum rate of the data transfer, with the rate being a function of all the possible input and output delays supported by the SoC. This is dependent on the parameters of the SoC. There is also a phase for programming a generic frequency converter between the first and second integrated processors for the data transfer, and a phase for scheduling the data transfer between the semi-synchronous clock domains.Type: ApplicationFiled: May 31, 2006Publication date: November 30, 2006Applicant: STMicroelectronics S.r.l.Inventors: Marco CASTANO, Salvatore PISASALE, Carmine CIOFI, Francesco GIOTTA
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Patent number: 7036038Abstract: A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.Type: GrantFiled: March 20, 2003Date of Patent: April 25, 2006Assignee: STMicroelectronics, S.r.l.Inventors: Ignazio UrzĂ, Massimiliano Fieni, Salvatore Pisasale
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Publication number: 20060041693Abstract: A decoupler that allows for asynchronous communication between two synchronous IP cores. The decoupler reduces or eliminates the need for distribution and balancing of the clock. More specifically, the decoupler provides the ability to decouple an IP core from the interconnect clock domain, thereby reducing the need for clock balancing. The decoupler is inserted between a source IP core and a target IP core, and may include two interfaces, one located near the source and another located near the target. Synchronous data messages are converted to asynchronous data messages for transmission across a physical connection. Once the asynchronous data message is received by the interface near the target or source, the data message is converted back to a synchronous message.Type: ApplicationFiled: May 27, 2004Publication date: February 23, 2006Applicant: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Salvatore Pisasale, Carmine Ciofi, Carmelo Pistritto
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Patent number: 6704821Abstract: An interconnect system includes an arbitration unit for arbitration among a plurality of sources or initiators requesting access to resources or targets. The arbitration unit selectively grants the initiators access to the targets as a function of respective priorities. The system includes a programmable control unit for programmably choosing the priorities in question out of group of at least two different priority schemes including a positional fixed priority, programmed fixed priority, and a variable priority based on a respective threshold latency values associated to the initiators.Type: GrantFiled: July 3, 2001Date of Patent: March 9, 2004Assignee: STMicroelectronics S.r.l.Inventors: Alberto Scandurra, Salvatore Pisasale
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Publication number: 20030198287Abstract: A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.Type: ApplicationFiled: March 20, 2003Publication date: October 23, 2003Applicant: STMicroelectronics S.r.l.Inventors: Ignazio Urzi, Massimiliano Fieni, Salvatore Pisasale
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Publication number: 20020069310Abstract: An interconnect system includes an arbitration unit for arbitration among a plurality of sources or initiators requesting access to resources or targets. The arbitration unit selectively grants the initiators access to the targets as a function of respective priorities. The system includes a programmable control unit for programmably choosing the priorities in question out of group of at least two different priority schemes including a positional fixed priority, programmed fixed priority, and a variable priority based on a respective threshold latency values associated to the initiators.Type: ApplicationFiled: July 3, 2001Publication date: June 6, 2002Applicant: STMicroelectronics S.r.l.Inventors: Alberto Scandurra, Salvatore Pisasale