Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.

Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.

Abstract: A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.

Abstract: A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.

Abstract: A memory device is configured for communicating with one of two different serial protocols, respectively an LPC or an SPI protocol, as well as with a parallel communication protocol through a multi-protocol interface while requiring only a single additional pin as compared to a standard memory device accessible with a parallel communication protocol. This result is achieved by exploiting the same pin for providing a timing signal for serial mode communications or an address multiplexing signal for parallel mode communications. The additional pin is used for conveying a start signal of an A/AMUX parallel communication protocol. The interface includes logic circuits that generate an enable signal for the standard memory core of the memory device.

Abstract: A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion may include a final stage with a complementary pair of MOS transistors inserted between two supply voltage references, and a third MOS transistor having its conduction terminals connected between one of the voltage references and an interconnection node of the complementary pair and receiving, on its control terminal, an activation pulse signal coming from a logic network incorporating at least one delay chain.

Abstract: An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

Abstract: The present invention relates to a non volatile memory device architecture, for example of the Flash type, incorporating a memory cell array and an input/output interface to receive memory data and/or addresses from and to the outside of the device. The interface operates generally according to a serial communication protocol, but it is equipped with a further pseudo-parallel communication portion with a low pin number incorporating circuit blocks for selecting the one or the other communication mode against an input-received selection signal.

Abstract: A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.

Abstract: A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion may include a final stage with a complementary pair of MOS transistors inserted between two supply voltage references, and a third MOS transistor having its conduction terminals connected between one of the voltage references and an interconnection node of the complementary pair and receiving, on its control terminal, an activation pulse signal coming from a logic network incorporating at least one delay chain.

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract: The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal. The array receives data from the state machine through the second internal bus and provides the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slave flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device includes a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

Abstract: The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal. Advantageously in the invention, a subsequent reading step is started also upon the fall edge of the control signal. In this way, at each cycle of the control signal two memory locations, instead of one as in the prior art, are read.

Abstract: The present invention relates to a non volatile memory device architecture, for example of the Flash type, incorporating a memory cell array and an input/output interface to receive memory data and/or addresses from and to the outside of the device. The interface operates generally according to a serial communication protocol, but it is equipped with a further pseudo-parallel communication portion with a low pin number incorporating circuit blocks for selecting the one or the other communication mode against an input-received selection signal.

Abstract: A memory device includes a multi-protocol interface having at least two interfaces. Each interface decodes a respective communication protocol when enabled by a respective interface enable signal. The memory device further includes an automatic selection circuit for selecting one of the interfaces corresponding to a received communication protocol. The automatic selection circuit compares bits transmitted during a preamble of a received communication protocol cycle with pre-established bit patterns corresponding to preambles of the communication protocols associated with the at least two interfaces, and generates an enable signal for one of the interfaces based upon the comparison.

Abstract: An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

Abstract: An architecture of a nonvolatile memory device, though not requiring dedicated pins and by introducing circuit modifications that require a negligible additional silicon area in the serial interface, allows a selection between at least two different serial communication protocols, thus multiplying the occasions of employment of the same device. The selection of one or of the another serial communication protocol is carried out by setting, during the testing on wafer (EWS) of the devices being fabricated, a certain UPROM cell of the array of UPROM cells that is normally present in a standard nonvolatile memory device for setting during the fabrication the characteristics of ATD, redundancy and other functions of the memory device. Alternatively, the customer can make the selection by placing an appropriate signal level on a specified pin of the memory device.

Abstract: A memory device includes a multi-protocol interface having at least two interfaces. Each interface decodes a respective communication protocol when enabled by a respective interface enable signal. The memory device further includes an automatic selection circuit for selecting one of the interfaces corresponding to a received communication protocol. The automatic selection circuit compares bits transmitted during a preamble of a received communication protocol cycle with pre-established bit patterns corresponding to preambles of the communication protocols associated with the at least two interfaces, and generates an enable signal for one of the interfaces based upon the comparison.