Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

Abstract: Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

Abstract: A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Abstract: There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: Methods of assembling a ball grid array (BGA) package is provided. One method includes providing a tape substrate that has a first surface and a second surface, attaching a first surface of a stiffener to the first substrate surface, mounting an IC die to the second stiffener surface, mounting a heat spreader to the IC die, and attaching a plurality of solder balls to the second substrate surface.

Abstract: Disclosed herein are systems, apparatuses, and methods for wirelessly coupling functional resources. Such a system includes a plurality of co-located, wireless-enabled functional units of a first type and a plurality of co-located, wireless-enabled functional units of a second type. At least one of the wireless-enabled functional units of the first type is wirelessly coupled with one or more of the wireless-enabled functional units of the second type. The wireless-enabled functional units of the first type may be wireless-enabled processing units, and the wireless-enabled functional units of the second type may be wireless-enabled memory units. In an example, the plurality of wireless-enabled functional units of the first type are co-located on a first chip, and the plurality of wireless-enabled functional units of the second type are co-located on a second chip. The first chip and the second chip may be located in a single device or in separate devices.

Abstract: In an embodiment, a thermal interface material (TIM) is provided. The TIM includes first and a second layers of a first transition metal, and a third layer including a plurality of carbon nanotubes supported in a flexible polymer matrix and a second transition metal coupled to sidewalls of carbon nanotubes. The first and second metal layers are in contact with first and second ends of carbon nanotube. The TIM further includes fourth and fifth layers of an alloy material coupled to the first and second metal layers, respectively. The carbon nanotube based TIM including the layers with transition metal allow improved heat transfer from an integrated circuit die to a heat spreader.

Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

Abstract: There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

Abstract: Embodiments of the present invention are directed to a wireless-enabled component (WEC) for enabling a wireless bus for intra-chip and inter-chip communication. A WEC encompasses a functional block of an IC (such as, for example, a processing core of a processing unit), an entire IC (such as, for example, a processing unit), or a device that includes a plurality of ICs (such as, for example, a handheld device). According to embodiments, a WEC may be associated with one or more sub-blocks of an IC, a single IC, or a plurality of ICs.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: Disclosed herein are systems, apparatuses, and methods for creating a system of wireless-enabled components (WECs). Such a system includes a server and a plurality of wireless-enabled component (WECs). Each WEC includes a functional resource (e.g., a processing resource and/or a memory resource) and is configured for wireless communication with the server and one or more other WECs. A first WEC is configured to wirelessly upload, to the server, an availability of the functional resource of the first WEC. The first WEC is further configured to wirelessly download, from the server, a linking resource for linking with one or more of the plurality of WECs. The plurality of WECs may be located on a single chip, on multiple chips of a single device, or on multiple chips of multiple devices.

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

Abstract: Embodiments of the present invention are directed to a scalable wireless bus for intra-chip and inter-chip communication. The scalable wireless bus includes a plurality of wireless-enabled components (WECs). In an embodiment, the scalable wireless bus may have at least one of the number of links among WECs and the capacity of said links adapted based on one or more factors. For example, the number of links and the capacity of the links may be adapted according to one or more of, among other factors, expected activity level over the wireless bus, desired power consumption, delay, and interference levels.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.