Abstract: A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.

Abstract: A physically unclonable function (PUF) device comprises a memory block including an array of cells, and a pseudo random number generator (PRNG) configured to generate a number of addresses to challenge the memory block in response to an element selected out of a combination.

Abstract: An on-line self-checking Hamming encoder is disclosed. The on-line self-checking Hamming encoder includes: a Hamming encoder, used to convert a received data vector into a Hamming codeword; and an error check unit, coupled to the Hamming encoder and used to generate a syndrome data vector of the Hamming codeword; wherein the on-line self-checking Hamming encoder generates an on-line self-checking result according to the syndrome. An on-line self-checking Hamming decoder and an associated method are also disclosed.

Abstract: A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.

Abstract: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure.

Abstract: A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode.

Abstract: A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM.

Abstract: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure.

Abstract: A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM.

Abstract: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.

Abstract: Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. At the same time, the compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.

Abstract: A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode.

Abstract: A method of self-testing and self-repairing a random access memory (RAM) is includes collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures. The method further includes performing obvious repair of failed cells during the collecting of the failure data and analyzing the failure data in the two FBM data structure to determine repair methods. The method further includes repairing failed cells of the RAM by using the redundant rows and columns.

Abstract: Mechanisms for self-testing and self-repairing memories are efficient in testing and repairing failed memory cells. The self-test-repair mechanisms are based on self-test results of failed bit map (FBM) data of the entire memories and enable early determination of non-repairable memories to prevent and limit wasting time and resources on non-repairable memories. The self-test-repair mechanisms also involve identifying candidates for column and row repairs and allow repeated repair cycles until either the memories are deemed irreparable or are fully repaired.

Abstract: A method of self-testing and self-repairing a random access memory (RAM) is includes collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures. The method further includes performing obvious repair of failed cells during the collecting of the failure data and analyzing the failure data in the two FBM data structure to determine repair methods. The method further includes repairing failed cells of the RAM by using the redundant rows and columns.

Abstract: Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. By performing obvious repair during collection of the FBM data, testing and date storage resources can be saved. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. The compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.