Abstract: Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. At the same time, the compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.

Abstract: Mechanisms for self-testing and self-repairing memories are efficient in testing and repairing failed memory cells. The self-test-repair mechanisms are based on self-test results of failed bit map (FBM) data of the entire memories and enable early determination of non-repairable memories to prevent and limit wasting time and resources on non-repairable memories. The self-test-repair mechanisms also involve identifying candidates for column and row repairs and allow repeated repair cycles until either the memories are deemed irreparable or are fully repaired.

Abstract: Failure bit map (FBM) data and a built-in-self-test-repair (BISTR) module enable collecting and analyzing FBM data of an entire memory to identify the best repairing method (or mechanism) to make repairs. By performing obvious repair during collection of the FBM data, testing and date storage resources can be saved. As a result, the repair method is better and more efficient than algorithms (or methods) known to the inventors, which only utilize partial (or incomplete) failure data. The compressed data structures used for the FBMs keep the resources used to capture the FBM data and to repair the failed cells relatively limited.

Abstract: A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.

Abstract: A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.

Abstract: A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.

Abstract: A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.

Abstract: A self-testable Digital Signal Processing (DSP) integrated circuit is described, using a Built-In Self Test (BIST) scheme suitable for high performance DSP datapaths. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DataPath-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan-based BIST technique is also presented. DP-BIST is used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.