Patents by Inventor Sameer Kumar

Sameer Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WEARABLE REPETITIVE BEHAVIOR AWARENESS DEVICE AND METHOD
    Publication number: 20210290131
    Abstract: The present disclosure relates generally to an awareness enhancement apparatus and method for undesirable repeated behaviors, including but not limited to obsessive compulsive and related disorders, and most relevant to trichotillomania (hair pulling), onychophagia (nail biting), dermatillomania (skin picking), and thumb sucking, among others. More particularly, the disclosure relates to a sensing and feedback device and associated methods of use which indicate a behavior based on the user's physical gestures and positioning of the hands, these gestures and positions being related to these undesirable behaviors typical of such disorders, and alerting the user so that he or she can reduce the behavior.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 23, 2021
    Inventors: Sameer Kumar, Aneela Idnani, John Pritchard, Kirk Klobe
  • Mapping 2-dimensional meshes on 3-dimensional torus
    Patent number: 11044169
    Abstract: In a L×M×N 3D torus network of computer nodes, a 2-dimensional plane comprising M×N torus network of nodes mapped into M/2 meshes×2*N torus network of nodes. N can be k*M, k is an integer greater than zero, and M and N are even numbers. Each of M/2 mesh of the 2*N torus is contiguous in the 2D plane. Mapping is performed for each of the L planes of the L×M×N 3D torus network. The M/2 meshes are combined with a remaining torus network dimension comprising L planes, the combining creating another 2*N pattern, wherein an L*M/2×2*N communication pattern is created. Application entities are executed according to the mapped L*M/2×2*N communication pattern.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Sameer Kumar
  • DEPENDENCY HANDLING FOR CONFIGURATION TRANSPORT
    Publication number: 20210182115
    Abstract: Systems and methods include reception of an indication of a first data object to transmit from a first database tenant to a second database tenant, the first data object comprising user configuration settings metadata of a database application and associated with a first data object type, determination of whether a dependent data object may be associated with a data object of the first data object type, determination, if it is determined that a dependent data object may be associated with a data object of the first data object type, of whether a dependent object is dependent on the first data object, and automatic determination, if it is determined that a dependent object is dependent on the first data object, to transmit the dependent object from the first database tenant to the second database tenant.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 17, 2021
    Inventors: Gaurav Loknath Gera, Martin Steiert, Martina Keller, Sameer Kumar, Thomas Gieselmann, Horst Schaude
  • Reliability processing of remote direct memory access
    Patent number: 10958588
    Abstract: Methods and systems for monitoring remote transmissions of messages among a plurality of nodes are described. A processing element in a first node may allocate a sequence number to a request to read and/or update data in a second node. The processing element may be different from main processors of the first node. The processing element may send the message and the sequence number to the second node. The processing element may modify a status of the sequence number to an active state, indicating a transmission of the message is pending. The processing element may, in response to a response from the second node, modify the status of the sequence number to an inactive state, indicating a completed transmission of the message. The processing element may, in response to no response from the second node within a time period, resend the message and the sequence number to the second node.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sameer Kumar, Philip Heidelberger, Yutaka Sugawara, Dong Chen, Robert M. Senger
  • CROSS REPLICA REDUCTION ON NETWORKS HAVING DEGRADED NODES
    Publication number: 20210049408
    Abstract: Methods, systems, and apparatus, including instructions encoded on storage media, for performing reduction of gradient vectors for a network having one or more degraded nodes. A method comprises training a respective replica of a machine learning model on each node of multiple nodes organized in an n-dimensional network topology, combining the respective individual gradient vectors in the nodes to generate a final gradient vector by performing operations comprising: designating each group of nodes along the dimension as either a forwarding group or a critical group, updating, for each receiving node, a respective individual gradient vector with an intermediate gradient vector, performing a reduction on each critical group of nodes along the dimension to generate a respective partial final gradient vector for the critical group, and updating, for each critical group of nodes, an individual gradient vector for a representative node with the respective partial final gradient vector.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Bjarke Hammersholt Roune, Sameer Kumar, Norman Paul Jouppi
  • Reduced number of counters for reliable messaging
    Patent number: 10812416
    Abstract: A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sameer Kumar, Philip Heidelberger, Dong Chen, Yutaka Sugawara, Robert M. Senger, Burkhard Steinmacher-Burow
  • Messaging software management for network devices supporting hardware tag matching
    Patent number: 10776185
    Abstract: Techniques are disclosed for efficient handling of messages in computing systems that include tag matching capable hardware. A message management module provides for handling message events including application receives and channel notifications such that hardware tag matching can continuously run in hardware channels, such as network adapters. When the message event is an application receive the message management module adds the application receive to a tracking queue and determines if the application receive can be posted to a hardware channel capable of tag matching. When the message event is a channel notification, the message management module determines a message action using the message tracking queue and the information in the channel notification.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sameh S. Sharkawi, Sameer Kumar, Bryan S. Rosenburg
  • MAPPING 2-DIMENSIONAL MESHES ON 3-DIMENSIONAL TORUS
    Publication number: 20200220787
    Abstract: In a L×M×N 3D torus network of computer nodes, a 2-dimensional plane comprising M×N torus network of nodes mapped into M/2 meshes×2*N torus network of nodes. N can be k*M, k is an integer greater than zero, and M and N are even numbers. Each of M/2 mesh of the 2*N torus is contiguous in the 2D plane. Mapping is performed for each of the L planes of the L×M×N 3D torus network. The M/2 meshes are combined with a remaining torus network dimension comprising L planes, the combining creating another 2*N pattern, wherein an L*M/2×2*N communication pattern is created. Application entities are executed according to the mapped L*M/2×2*N communication pattern.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Dong Chen, Sameer Kumar
  • MESSAGING SOFTWARE MANAGEMENT FOR NETWORK DEVICES SUPPORTING HARDWARE TAG MATCHING
    Publication number: 20200183764
    Abstract: Techniques are disclosed for efficient handling of messages in computing systems that include tag matching capable hardware. A message management module provides for handling message events including application receives and channel notifications such that hardware tag matching can continuously run in hardware channels, such as network adapters. When the message event is an application receive the message management module adds the application receive to a tracking queue and determines if the application receive can be posted to a hardware channel capable of tag matching. When the message event is a channel notification, the message management module determines a message action using the message tracking queue and the information in the channel notification.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventors: Sameh S. SHARKAWI, Sameer KUMAR, Bryan S. ROSENBURG
  • TRAINING NEURAL NETWORKS USING DISTRIBUTED BATCH NORMALIZATION
    Publication number: 20200125949
    Abstract: Methods, systems, and apparatus, including instructions encoded on storage media, for performing reduction of gradient vectors for distributed training of a neural network. One of the methods includes receiving, at each of the plurality of devices, a respective batch; performing, by each device, a forward pass comprising, for each batch normalization layer: generating, by each of the devices, a respective output of the corresponding other layer for each training example in the batch, determining, by each of the devices, a per-replica mean and a per-replica variance; determining, for each sub-group, a distributed mean and a distributed variance from the per-replica means and the per-replica variances for the devices in the sub-group; and applying, by each device, batch normalization to the respective outputs of the corresponding other layer generated by the device using the distributed mean and the distributed variance for the sub-group to which the device belongs.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 23, 2020
    Inventors: Blake Alan Hechtman, Sameer Kumar
  • Asynchronous stochastic gradient descent
    Patent number: 10628740
    Abstract: The example computer-implemented method may comprise computing, by a generator processor on each of a plurality of learners, a gradient for a mini-batch using a current weight at each of the plurality of learners. The method may also comprise generating, by the generator processor on each of the plurality of learners, a plurality of triples, wherein each of the triples comprises the gradient, the weight index of the current weights used to compute the gradient, and a mass of the gradient. The method may further comprise performing, by a reconciler processor on each of the plurality of learners, an allreduce operation on the plurality of triples to obtain an allreduced triple sequence. Additionally, the method may comprise updating, by the reconciler processor on each of the plurality of learners, the current weight at each of the plurality of learners to a new current weight using the allreduced triple sequence.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameer Kumar, Vijay A. Saraswat
  • RELIABILITY PROCESSING OF REMOTE DIRECT MEMORY ACCESS
    Publication number: 20190245799
    Abstract: Methods and systems for monitoring remote transmissions of messages among a plurality of nodes are described. A processing element in a first node may allocate a sequence number to a request to read and/or update data in a second node. The processing element may be different from main processors of the first node. The processing element may send the message and the sequence number to the second node. The processing element may modify a status of the sequence number to an active state, indicating a transmission of the message is pending. The processing element may, in response to a response from the second node, modify the status of the sequence number to an inactive state, indicating a completed transmission of the message. The processing element may, in response to no response from the second node within a time period, resend the message and the sequence number to the second node.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Inventors: Sameer Kumar, Philip Heidelberger, Yutaka Sugawara, Dong Chen, Robert M. Senger
  • REDUCED NUMBER OF COUNTERS FOR RELIABLE MESSAGING
    Publication number: 20190199653
    Abstract: A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Inventors: Sameer Kumar, Philip Heidelberger, Dong Chen, Yutaka Sugawara, Robert M. Senger, Burkhard Steinmacher-Burow
  • BROWSER-BASED GENERATION OF NEW LOGICAL DATA OBJECTS
    Publication number: 20180164967
    Abstract: A method of customizing a computing environment comprises providing a browser-based application to a user, receiving instructions from the user via the browser-based application to define a custom logical data object, defining the custom logical data object in a system backend in accordance with the instructions, and generating a user interface comprising the custom logical data object within the browser-based application.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Applicant: SAP SE
    Inventors: Pradeep Kumar N, Prabhat Raman, Sreekanth K, Jitender Bhatia, Horst Schaude, Bhavani Shankar Indrakanti, Abhishek Kunuthur Naga, Duroc Marie Denise Duroc Andre, Prabhu Mallappa Yandigeri, Manjunath Jn, Prathiba Aravind, Nikita Jain, Sameer Kumar, Sasi Kanth Velagaleti, Aravinda Pantar
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Mechanism to extend the remote get to do async rectangle broadcast on a rectangle with wild cards in the packet header
    Patent number: 9948543
    Abstract: A method (and structure) for improving efficiency in a multiprocessor system including a plurality of processor nodes interconnected in a multidimensional array, each processor node including a processor, an associated memory device, and an associated inter-nodal interface device for exchange of data with other nodes. Each processor can implement a broadcast procedure as an initiator node, using a format that permits inter-nodal interface devices at each node receiving a broadcast instruction packet to process the received broadcast instruction packet without using processing resources of the processor at the receiving node. Each inter-nodal interface device in each node can implement the broadcast procedure without using processing resources of the processor associated with the receiving node.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Philip Heidelberger, Sameer Kumar
  • MECHANISM TO EXTEND THE REMOTE GET TO DO ASYNC RECTANGLE BROADCAST ON A RECTANGLE WITH WILD CARDS IN THE PACKET HEADER
    Publication number: 20170195212
    Abstract: A method (and structure) for improving efficiency in a multiprocessor system including a plurality of processor nodes interconnected in a multidimensional array, each processor node including a processor, an associated memory device, and an associated inter-nodal interface device for exchange of data with other nodes. Each processor can implement a broadcast procedure as an initiator node, using a format that permits inter-nodal interface devices at each node receiving a broadcast instruction packet to process the received broadcast instruction packet without using processing resources of the processor at the receiving node. Each inter-nodal interface device in each node can implement the broadcast procedure without using processing resources of the processor associated with the receiving node.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Dong Chen, Philip Heidelberger, Sameer Kumar
  • Performing synchronized collective operations over multiple process groups
    Patent number: 9665532
    Abstract: Methods and arrangements for performing synchronized collective operations. Communication calls are accepted from at least two distinct processor groups. Edge disjoint spanning paths are created over a collective comprising the processor groups, and the spanning paths are assigned to the processor groups to facilitate communication within each processor group.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas George, Nikhil Jain, Sameer Kumar, Anshul Mittal, Yogish Sabharwal
  • Performing synchronized collective operations over multiple process groups
    Patent number: 9665531
    Abstract: Methods and arrangements for performing synchronized collective operations. Communication calls are accepted from at least two distinct processor groups. Edge disjoint spanning paths are created over a collective comprising the processor groups, and the spanning paths are assigned to the processor groups to facilitate communication within each processor group.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas George, Nikhil Jain, Sameer Kumar, Anshul Mittal, Yogish Sabharwal
  • ASYNCHRONOUS STOCHASTIC GRADIENT DESCENT
    Publication number: 20170098171
    Abstract: The example computer-implemented method may comprise computing, by a generator processor on each of a plurality of learners, a gradient for a mini-batch using a current weight at each of the plurality of learners. The method may also comprise generating, by the generator processor on each of the plurality of learners, a plurality of triples, wherein each of the triples comprises the gradient, the weight index of the current weights used to compute the gradient, and a mass of the gradient. The method may further comprise performing, by a reconciler processor on each of the plurality of learners, an allreduce operation on the plurality of triples to obtain an allreduced triple sequence. Additionally, the method may comprise updating, by the reconciler processor on each of the plurality of learners, the current weight at each of the plurality of learners to a new current weight using the allreduced triple sequence.
    Type: Application
    Filed: May 5, 2016
    Publication date: April 6, 2017
    Inventors: Sameer Kumar, VIJAY A. SARASWAT