Patents by Inventor Sameer Kumar

Sameer Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mechanism to extend the remote get to do async rectangle broadcast on a rectangle with wild cards in the packet header
    Patent number: 9948543
    Abstract: A method (and structure) for improving efficiency in a multiprocessor system including a plurality of processor nodes interconnected in a multidimensional array, each processor node including a processor, an associated memory device, and an associated inter-nodal interface device for exchange of data with other nodes. Each processor can implement a broadcast procedure as an initiator node, using a format that permits inter-nodal interface devices at each node receiving a broadcast instruction packet to process the received broadcast instruction packet without using processing resources of the processor at the receiving node. Each inter-nodal interface device in each node can implement the broadcast procedure without using processing resources of the processor associated with the receiving node.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Philip Heidelberger, Sameer Kumar
  • Wearable repetitive behavior awareness device and method
    Patent number: 9721450
    Abstract: The present invention relates generally to an awareness enhancement apparatus and method for undesirable repeated behaviors, including but not limited to obsessive compulsive and related disorders, and most relevant to trichotillomania (hair pulling), onychophagia (nail biting), dermatillomania (skin picking) and thumb sucking, among others. More particularly, the invention relates to a sensing and feedback device and associated methods of use which indicates a behavior based on the user's physical gestures and positioning of the hands, these gestures and positions being related to these undesirable behaviors typical of such disorders and alerting the user so that he or she can reduce the behavior.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 1, 2017
    Inventor: Sameer A. Kumar
  • MECHANISM TO EXTEND THE REMOTE GET TO DO ASYNC RECTANGLE BROADCAST ON A RECTANGLE WITH WILD CARDS IN THE PACKET HEADER
    Publication number: 20170195212
    Abstract: A method (and structure) for improving efficiency in a multiprocessor system including a plurality of processor nodes interconnected in a multidimensional array, each processor node including a processor, an associated memory device, and an associated inter-nodal interface device for exchange of data with other nodes. Each processor can implement a broadcast procedure as an initiator node, using a format that permits inter-nodal interface devices at each node receiving a broadcast instruction packet to process the received broadcast instruction packet without using processing resources of the processor at the receiving node. Each inter-nodal interface device in each node can implement the broadcast procedure without using processing resources of the processor associated with the receiving node.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Dong Chen, Philip Heidelberger, Sameer Kumar
  • Performing synchronized collective operations over multiple process groups
    Patent number: 9665531
    Abstract: Methods and arrangements for performing synchronized collective operations. Communication calls are accepted from at least two distinct processor groups. Edge disjoint spanning paths are created over a collective comprising the processor groups, and the spanning paths are assigned to the processor groups to facilitate communication within each processor group.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas George, Nikhil Jain, Sameer Kumar, Anshul Mittal, Yogish Sabharwal
  • Performing synchronized collective operations over multiple process groups
    Patent number: 9665532
    Abstract: Methods and arrangements for performing synchronized collective operations. Communication calls are accepted from at least two distinct processor groups. Edge disjoint spanning paths are created over a collective comprising the processor groups, and the spanning paths are assigned to the processor groups to facilitate communication within each processor group.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas George, Nikhil Jain, Sameer Kumar, Anshul Mittal, Yogish Sabharwal
  • METHOD FOR LOCKING AND UNLOCKING TOUCHSCREEN-EQUIPPED MOBILE DEVICE AND MOBILE DEVICE
    Publication number: 20170109035
    Abstract: The present disclosure relates generally to technologies for sensor networks, machine-to-machine (M2M), machine-type communication (MTC), and Internet of things (IoT). The present disclosure may be used in intelligent services (smart home, smart building, smart city, smart car, or connected car, health-care, digital education, retail business, security and safety-related services, etc.), or the like, without limitation.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Pankaj AGARWAL, Sameer Kumar AGRAWAL, Parichay KAPOOR
  • ASYNCHRONOUS STOCHASTIC GRADIENT DESCENT
    Publication number: 20170098171
    Abstract: The example computer-implemented method may comprise computing, by a generator processor on each of a plurality of learners, a gradient for a mini-batch using a current weight at each of the plurality of learners. The method may also comprise generating, by the generator processor on each of the plurality of learners, a plurality of triples, wherein each of the triples comprises the gradient, the weight index of the current weights used to compute the gradient, and a mass of the gradient. The method may further comprise performing, by a reconciler processor on each of the plurality of learners, an allreduce operation on the plurality of triples to obtain an allreduced triple sequence. Additionally, the method may comprise updating, by the reconciler processor on each of the plurality of learners, the current weight at each of the plurality of learners to a new current weight using the allreduced triple sequence.
    Type: Application
    Filed: May 5, 2016
    Publication date: April 6, 2017
    Inventors: Sameer Kumar, VIJAY A. SARASWAT
  • WEARABLE REPETITIVE BEHAVIOR AWARENESS DEVICE AND METHOD
    Publication number: 20160247380
    Abstract: The present invention relates generally to an awareness enhancement apparatus and method for undesirable repeated behaviors, including but not limited to obsessive compulsive and related disorders, and most relevant to trichotillomania (hair pulling), onychophagia (nail biting), dermatillomania (skin picking) and thumb sucking, among others. More particularly, the invention relates to a sensing and feedback device and associated methods of use which indicates a behavior based on the user's physical gestures and positioning of the hands, these gestures and positions being related to these undesirable behaviors typical of such disorders and alerting the user so that he or she can reduce the behavior.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 25, 2016
    Inventor: Sameer A. KUMAR
  • Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator
    Patent number: 9244734
    Abstract: A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality of communicators for storing state information for a barrier algorithm. Each communicator designates a master core in a multi-processor environment of the computer system. The system allocates or designates one counter for each of a plurality of threads. The system configures a table with a number of entries equal to the maximum number of threads. The system sets a table entry with an ID associated with a communicator when a process thread initiates a collective. The system determines an allocated or designated counter by searching entries in the table.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Blocksome, Sameer Kumar, Amith R. Mamidala, Douglas Miller, Joseph D. Ratterman
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Processing posted receive commands in a parallel computer
    Patent number: 9158602
    Abstract: Processing posted receive commands in a parallel computer, including: posting, by a parallel process of a compute node, a receive command, the receive command including a set of parameters excluding the receive command from being directed among parallel posted receive queues; flattening the parallel unexpected message queues into a single unexpected message queue; determining whether the posted receive command is satisfied by an entry in the single unexpected message queue; if the posted receive command is satisfied by an entry in the single unexpected message queue, processing the posted receive command; if the posted receive command is not satisfied by an entry in the single unexpected message queue: flattening the parallel posted receive queues into a single posted receive queue; and storing the posted receive command in the single posted receive queue.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: October 13, 2015
    Assignee: Intermational Business Machines Corporation
    Inventors: Sameer Kumar, Amith R. Mamidala, Joseph D. Ratterman, Brian E. Smith
  • Processing posted receive commands in a parallel computer
    Patent number: 9152481
    Abstract: Processing posted receive commands in a parallel computer, including: posting, by a parallel process of a compute node, a receive command, the receive command including a set of parameters excluding the receive command from being directed among parallel posted receive queues; flattening the parallel unexpected message queues into a single unexpected message queue; determining whether the posted receive command is satisfied by an entry in the single unexpected message queue; if the posted receive command is satisfied by an entry in the single unexpected message queue, processing the posted receive command; if the posted receive command is not satisfied by an entry in the single unexpected message queue: flattening the parallel posted receive queues into a single posted receive queue; and storing the posted receive command in the single posted receive queue.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sameer Kumar, Amith R. Mamidala, Joseph D. Ratterman, Brian E. Smith
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Brand Scoring for Social Media Users
    Publication number: 20150149373
    Abstract: Techniques for brand scoring for social media users are described. In at least some embodiments, brand-related content that users post to a social media environment (e.g., social media website(s)) is identified and characterized. Based on attributes of a user and brand-related content posted by the user, a brand score for the user may be calculated. In at least some embodiments, a user's brand score provides an indication of the user's perception of a brand and/or the user's influence on perception of the brand in a social media environment.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: ADOBE SYSTEMS INCORPORATED
    Inventors: Niyati Himanshu Chhaya, Sameer Kumar Agrawal, Vikram Singh Rathore, Tushar Mehndiratta
  • PROCESS FOR PREPARATION OF IRON SUCROSE
    Publication number: 20150141630
    Abstract: The present invention is directed to processes for preparation of iron sucrose complex and purification of the obtained iron sucrose through diafiltration.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 21, 2015
    Inventors: Amit Biswas, Vilas Dahanukar, Elati Ravi Ram Chandrasekar, Mohanarangam Saravanan, Penumandla Raja Gopal, Chandra Sekhar Vempati, Kushal Surajmal Manudhane, Ande Sameer Kumar
  • Store-operate-coherence-on-value
    Patent number: 8892824
    Abstract: A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Philip Heidelberger, Sameer Kumar, Martin Ohmacht, Burkhard Steinmacher-Burow
  • Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives
    Patent number: 8838944
    Abstract: Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving high performance. In another aspect, new synchronization primitives FetchAndIncrementBounded (Counter, Bound) and FetchAndDecrementBounded (Counter, Bound) are implemented. These primitives can be implemented in hardware and thus promise a very fast throughput for queues, stacks and double-ended queues.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Alana Gara, Philip Heidelberger, Sameer Kumar, Martin Ohmacht, Burkhard Steinmacher-Burow, Robert Wisniewski
  • Implementing asyncronous collective operations in a multi-node processing system
    Patent number: 8782164
    Abstract: A method, system, and computer program product are disclosed for implementing an asynchronous collective operation in a multi-node data processing system. In one embodiment, the method comprises sending data to a plurality of nodes in the data processing system, broadcasting a remote get to the plurality of nodes, and using this remote get to implement asynchronous collective operations on the data by the plurality of nodes. In one embodiment, each of the nodes performs only one task in the asynchronous operations, and each nodes sets up a base address table with an entry for a base address of a memory buffer associated with said each node. In another embodiment, each of the nodes performs a plurality of tasks in said collective operations, and each task of each node sets up a base address table with an entry for a base address of a memory buffer associated with the task.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Noel A. Eisley, Philp Heidelberger, Sameer Kumar, Valentina Salapura, Burkhard Steinmacher-Burow
  • Completion processing for data communications instructions
    Patent number: 8775531
    Abstract: Completion processing of data communications instructions in a distributed computing environment with computers coupled for data communications through communications adapters and an active messaging interface (‘AMI’), injecting for data communications instructions into slots in an injection FIFO buffer a transfer descriptor, at least some of the instructions specifying callback functions; injecting a completion descriptor for each instruction that specifies a callback function into an injection FIFO buffer slot having a corresponding slot in a pending callback list; listing in the pending callback list callback functions specified by data communications instructions; processing each descriptor in the injection FIFO buffer, setting a bit in a completion bit mask corresponding to the slot in the FIFO where the completion descriptor was injected; and calling by the AMI any callback functions in the pending callback list as indicated by set bits in the completion bit mask.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blocksome, Sameer Kumar, Jeffrey J. Parker
  • Completion processing for data communications instructions
    Patent number: 8751595
    Abstract: Completion processing of data communications instructions in a distributed computing environment with computers coupled for data communications through communications adapters and an active messaging interface (‘AMI’), injecting for data communications instructions into slots in an injection FIFO buffer a transfer descriptor, at least some of the instructions specifying callback functions; injecting a completion descriptor for each instruction that specifies a callback function into an injection FIFO buffer slot having a corresponding slot in a pending callback list; listing in the pending callback list callback functions specified by data communications instructions; processing each descriptor in the injection FIFO buffer, setting a bit in a completion bit mask corresponding to the slot in the FIFO where the completion descriptor was injected; and calling by the AMI any callback functions in the pending callback list as indicated by set bits in the completion bit mask.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blocksome, Sameer Kumar, Jeffrey J. Parker