Abstract: Disclosed is a mechanism on receiving processors in a parallel computing system for providing order to data packets received from a broadcast call and to distinguish data packets received at nodes from several incoming asynchronous broadcast messages where header space is limited. In the present invention, processors at lower leafs of a tree do not need to obtain a broadcast message by directly accessing the data in a root processor's buffer. Instead, each subsequent intermediate node's rank id information is squeezed into the software header of packet headers. In turn, the entire broadcast message is not transferred from the root processor to each processor in a communicator but instead is replicated on several intermediate nodes which then replicated the message to nodes in lower leafs. Hence, the intermediate compute nodes become “virtual root compute nodes” for the purpose of replicating the broadcast message to lower levels of a tree.

Abstract: A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node.

Abstract: A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.

Abstract: Methods, compute nodes, and computer program products are provided for heuristic status polling of a component in a computing system. Embodiments include receiving, by a polling module from a requesting application, a status request requesting status of a component; determining, by the polling module, whether an activity history for the component satisfies heuristic polling criteria; polling, by the polling module, the component for status if the activity history for the component satisfies the heuristic polling criteria; and not polling, by the polling module, the component for status if the activity history for the component does not satisfy the heuristic criteria.

Abstract: Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

Abstract: A printed circuit board assembly utilizing an elevated track to support signal lines between components is disclosed. The track rests on a plurality of vertical supports, placed amid the components, such that the signal lines can be routed after the components are configured on the board. The vertical supports can be installed at grounding holes already present on the printed circuit board assembly. The track is sufficiently rigid to support bundles of signal lines over long spans between vertical supports. The track can be constructed of the same material as the board, to provide the same ESD and conductivity characteristics as the board, as well as ensure that the track does not contribute to the EMI signature of the board.

Abstract: A method of achieving route optimization (RO) when a dual capable mobile Internet protocol version 6 (MIPv6) mobile node is connected with an IPv4-only network allows RO of packets to traverse a shorter route than the default one through the home agent (HA) using bidirectional tunneling, and leads to better bandwidth utilization. The method of RO with a dual MIPV6 node in an IPV4-only network includes updating the HA with an IPv4 address of the MN and deregistering a binding update (BU) with a corresponding node (CN) via the HA; informing the CN about its IPv4 address and receiving the CN's IPv4 address in reply; checking reachability of the CN in its IPv4 address using an IPv6-in-IPv4 tunnel; and sending and receiving Ipv6 data packets to/from the CN using a v4 tunnel.

Abstract: A method for route optimization with a dual mobile IPv4 node in an IPv6-only network is provided. The method includes the operations of: receiving a visited IPv6 address from a router when the dual mobile node is connected to the IPv6-only network; updating a home agent with the IPv6 address; deregistering a binding update with a correspondent node via the home agent; updating the correspondent node with an IPv6 address; checking the reachability of packets directly to the correspondent node using its IPv6 address; the mobile node starting sending, to the CN, data packets tunneled in an IPv6 packet once the reachability is verified; and the correspondent node sending tunneled data packets directly to an IPv6 address of the mobile node.

Abstract: A method and an apparatus to speed up fast mobile internet protocol version 6 (FMIPv6) by using a relatively fast layer 2 handover. A method and an apparatus to use FMIPv6 to trigger a relatively fast layer 2 handover of a mobile node from an initial access point associated with a previous access router to a neighboring access point associated with a next access router.

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).