Patents by Inventor Sameer PAITAL

Sameer PAITAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12635540
    Abstract: Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: May 19, 2026
    Assignee: Intel Corporation
    Inventors: Sameer Paital, Gang Duan, Srinivas V. Pietambaram, Kristof Kuwawi Darmawikarta, Tchefor Ndukum, Vejayakumaran Padavettan, Pooja Wadhwa, Brandon C. Marin
  • Patent number: 12568831
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: March 3, 2026
    Assignee: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
  • Patent number: 12517314
    Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 6, 2026
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Brandon C. Marin, Sameer Paital, Sai Vadlamani, Rahul N. Manepalli, Xiaoqian Li, Suresh V. Pothukuchi, Sujit Sharan, Arnab Sarkar, Omkar Karhade, Nitin Deshpande, Divya Pratap, Jeremy Ecton, Debendra Mallik, Ravindranath V. Mahajan, Zhichao Zhang, Kemal Aygün, Bai Nie, Kristof Darmawikarta, James E. Jaussi, Jason M. Gamba, Bryan K. Casper, Gang Duan, Rajesh Inti, Mozhgan Mansuri, Susheel Jadhav, Kenneth Brown, Ankur Agrawal, Priyanka Dobriyal
  • Publication number: 20250323166
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: June 23, 2025
    Publication date: October 16, 2025
    Applicant: Intel Corporation
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Patent number: 12354963
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 12334443
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: June 17, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Publication number: 20250112138
    Abstract: Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Sameer Paital, Zhixin Xie, Rahul Manepalli, Jieying Kong
  • Publication number: 20250112163
    Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Pratyush Mishra, Pratyasha Mohapatra, Srinivas Pietambaram, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Yosef Kornbluth, Kuang Liu, Astitva Tripathi, Yuqin Li, Rengarajan Shanmugam, Xing Sun, Brian Balch, Darko Grujicic, Jieying Kong, Nicholas Haehn, Jacob Vehonsky, Mitchell Page, Vincent Obiozo Eze, Daniel Wandera, Sameer Paital, Gang Duan
  • Patent number: 12230430
    Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Kristof Darmawikarta, Gang Duan, Yonggang Li, Sameer Paital
  • Publication number: 20240421043
    Abstract: Various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 19, 2024
    Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Ji Yong Park, Kyu Oh Lee, Sheng Li, Gang Duan, Sameer Paital
  • Publication number: 20240243066
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Publication number: 20240222282
    Abstract: Apparatuses, systems, assemblies, and techniques related to forming a metallization structure in a glass core package substrate such that the metallization structure has multiple portions with differing cross-sectional widths with little or no misalignment between the portions are described. Such techniques including mounting the glass core substrate to a stage, applying multiple laser exposures to a location of the glass core substrate to define laser treated regions of the glass core substrate corresponding to the portions of the metallization structure, removing the laser treated regions, and filling the openings with metal to form the embedded zero misaligned metallization structure.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Kristof Darmawikarta
  • Publication number: 20240178145
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Publication number: 20240114623
    Abstract: An electronic device includes a substrate including a glass core layer and first contact pads on a first surface of the glass core layer; one or more discrete passive electronic components disposed on the first surface of the glass core layer, the one or more discrete passive electronic components including second contact pads on a bottom surface of the one or more discrete passive electronic components; and hybrid bonds between the first contact pads of the glass core layer and the second contact pads of the one or more discrete passive electronic components.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Sameer Paital
  • Publication number: 20240088052
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
  • Patent number: 11929330
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 11929212
    Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Kristof Darmawikarta
  • Patent number: 11923312
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
  • Publication number: 20230420378
    Abstract: Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Gang Duan, Srinivas V. Pietambaram, Kristof Kuwawi Darmawikarta, Tchefor Ndukum, Vejayakumaran Padavettan, Pooja Wadhwa, Brandon C. Marin
  • Publication number: 20230420357
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Brandon C. MARIN, Suddhasattwa NAD, Srinivas V. PIETAMBARAM, Gang DUAN, Jeremy D. ECTON, Kristof DARMAWIKARTA, Sameer PAITAL