Patents by Inventor Sameer PAITAL

Sameer PAITAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227849
    Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Srinivas V. Pietambaram, Kristof Darmawikarta, Gang Duan, Sameer Paital
  • Publication number: 20210091030
    Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: Brandon C. Marin, Srinivas V. Pietambaram, Kristof Darmawikarta, Gang Duan, Sameer Paital
  • Publication number: 20200343049
    Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Sameer PAITAL, Gang DUAN, Srinivas PIETAMBARAM, Kristof DARMAWIKARTA
  • Publication number: 20200312771
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
  • Publication number: 20200091053
    Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Srinivas V. Pietambaram, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Krishna Bharath, Michael James Hill
  • Publication number: 20200083164
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Brandon C. MARIN, Frank TRUONG, Shivasubramanian BALASUBRAMANIAN, Dilan SENEVIRATNE, Yonggang LI, Sameer PAITAL, Darko GRUJICIC, Rengarajan SHANMUGAM, Melissa WETTE, Srinivas PIETAMBARAM
  • Publication number: 20200005990
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Sameer PAITAL, Srinivas PIETAMBARAM, Yonggang LI, Bai NIE, Kristof DARMAWIKARTA, Gang DUAN
  • Publication number: 20200005987
    Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Srinivas Pietambaram, Kristof Darmawikarta, Gang Duan, Yonggang Li, Sameer Paital
  • Publication number: 20190295951
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Publication number: 20190279806
    Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Inventors: Kristof DARMAWIKARTA, Srinivas PIETAMBARAM, Sandeep GAAN, Sri Ranga Sai BOYAPATI, Prithwish CHATTERJEE, Sameer PAITAL, Rahul JAIN, Junnan ZHAO