Patents by Inventor Sameer S. Pradhan
Sameer S. Pradhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230028568Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Applicant: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Patent number: 10998445Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: GrantFiled: May 18, 2020Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Sameer S. Pradhan, Jeanne L. Luce
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Publication number: 20200357916Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Applicant: Intel CorporationInventors: Sameer S. PRADHAN, Subhash M. JOSHI, Jin-Sung CHUN
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Patent number: 10770591Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: GrantFiled: March 21, 2019Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20200279950Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Applicant: Intel CorporationInventors: Sameer S. Pradhan, Jeanne L. Luce
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Publication number: 20190221662Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Applicant: Intel CorporationInventors: Sameer S. PRADHAN, Subhash M. JOSHI, Jin-Sung CHUN
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Patent number: 10283640Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: GrantFiled: July 21, 2017Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Patent number: 10020375Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: October 6, 2017Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Publication number: 20180047825Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: October 6, 2017Publication date: February 15, 2018Applicant: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9853156Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: GrantFiled: February 10, 2015Date of Patent: December 26, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20170323966Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: July 21, 2017Publication date: November 9, 2017Applicant: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Patent number: 9812546Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: January 9, 2017Date of Patent: November 7, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9637810Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: September 21, 2015Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Publication number: 20170117378Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: January 9, 2017Publication date: April 27, 2017Applicant: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9580776Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: September 21, 2015Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9490347Abstract: The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.Type: GrantFiled: October 28, 2015Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Aaron W. Rosenbaum, Din-How Mei, Sameer S. Pradhan
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Patent number: 9425316Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: GrantFiled: December 17, 2015Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20160111532Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: December 17, 2015Publication date: April 21, 2016Applicant: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20160049499Abstract: The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.Type: ApplicationFiled: October 28, 2015Publication date: February 18, 2016Applicant: INTEL CORPORATIONInventors: Aaron W. Rosenbaum, Din-How Mei, Sameer S. Pradhan
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Publication number: 20160035724Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: September 21, 2015Publication date: February 4, 2016Applicant: INTEL CORPORATIONInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
