Abstract: Certain aspects of the present disclosure provide techniques and apparatus for performing mathematical operations on a processor. The method generally includes initializing at least a portion of weight data for a machine learning model in a first memory component associated with a processor. Input data is stored in a second memory component coupled with the processor. Operations using the machine learning model are executed, via a functional unit associated with the processor, based on the at least the portion of the weight data and the input data. A result of the operations using the machine learning model are stored in the second memory component.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay cell.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: Methods and apparatus for supplying power to a dynamic load, such as a neural network circuit. One example power supply circuit generally includes a voltage regulator circuit and a distribution circuit coupled to one or more outputs of the voltage regulator circuit. The distribution circuit is configured to output different amounts of current based on changes in the dynamic load. For certain aspects, the dynamic load includes a neural network circuit having a plurality of segments. In this case, the distribution circuit may be configured to output the different amounts of current based on which segment in the plurality of segments of the neural network circuit is active.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

Abstract: Certain aspects of the present disclosure provide techniques for efficient depthwise convolution. A convolution is performed with a compute-in-memory (CIM) array to generate CIM output, and at least a portion of the CIM output corresponding to a first output data channel, of a plurality of output data channels in the CIM output, is written to a digital multiply-accumulate (DMAC) activation buffer. A patch of the CIM output is read from the DMAC activation buffer, and weight data is read from a DMAC weight buffer. Multiply-accumulate (MAC) operations are performed with the patch of CIM output and the weight data to generate a DMAC output.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Abstract: Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for capacitance modulation to mitigate pixel leakage in ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor including a column line, a pixel having a transistor coupled to the column line, a pixel control circuit coupled to a drain the transistor of the pixel. The ultrasonic sensor may also include a column control circuit coupled to a source of the transistor, wherein at least one of the pixel control circuit or the column control circuit is configured to couple at least one of the drain or the source of the transistor, respectively, to an electric ground during a hold phase of the ultrasonic sensor, and a receiver circuit coupled to the column line.

Abstract: A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

Abstract: Certain aspects of the present disclosure provide techniques for look-ahead column sensing for fast voltage-mode read on ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor that generally includes a column line, a pixel having a transistor coupled between a voltage rail and the column line, a receiver circuit, and a first column control circuit coupled between the receiver circuit and the pixel, the first column control circuit being configured to electrically isolate the column line from the receiver circuit during a look-ahead settling phase of the ultrasonic sensor, and electrically couple the column line to the receiver circuit during a sensing phase of the ultrasonic sensor.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for capacitance modulation to mitigate pixel leakage in ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor including a column line, a pixel having a transistor coupled to the column line, a pixel control circuit coupled to a drain the transistor of the pixel. The ultrasonic sensor may also include a column control circuit coupled to a source of the transistor, wherein at least one of the pixel control circuit or the column control circuit is configured to couple at least one of the drain or the source of the transistor, respectively, to an electric ground during a hold phase of the ultrasonic sensor, and a receiver circuit coupled to the column line.

Abstract: Certain aspects of the present disclosure provide techniques for look-ahead column sensing for fast voltage-mode read on ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor that generally includes a column line, a pixel having a transistor coupled between a voltage rail and the column line, a receiver circuit, and a first column control circuit coupled between the receiver circuit and the pixel, the first column control circuit being configured to electrically isolate the column line from the receiver circuit during a look-ahead settling phase of the ultrasonic sensor, and electrically couple the column line to the receiver circuit during a sensing phase of the ultrasonic sensor.

Abstract: Disclosed are techniques for sensing an ultrasonic signal. In aspects, a pixel circuit includes a first switch coupled to a first input signal configured to drive the first switch, a second switch coupled to a second input signal configured to drive the second switch, a capacitor coupled to the first switch and the second switch and configured to detect the ultrasonic signal, an output device coupled to the second switch and a power supply for the pixel circuit, wherein the output device is configured to store an input signal from the capacitor, wherein the input signal from the capacitor is received at the output device from the second switch, and an output switch coupled to the output device and a column of a pixel array, wherein the output device is configured to output the input signal to the column of the pixel array based on activation of the output switch.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: An ultrasonic fingerprint sensor system of the present disclosure may be provided with an ultrasonic transmitter or ultrasonic transceiver having an electrode layer divided into a plurality of electrode segments. The ultrasonic fingerprint sensor system may detect an object over one or more electrode segments and provide a voltage burst to one or more selected electrode segments for localized generation of ultrasonic waves. The localized generation of ultrasonic waves may facilitate localized readout for imaging. In some implementations, the voltage burst may be provided in a single-ended drive scheme or differential drive scheme.