Abstract: A method for calibrating an output driver includes generating a first current representative of current flowing through a termination impedance of an output driver, generating a second current representative of current flowing through a replica driver stage comprising one or more replicas of a driver stage in a driver segment in the output driver, and comparing the first current and the second current using a current comparator. Generating the second current includes controlling gate voltage of first transistors configured to provide a reference current to the replica driver stage to maintain a predefined voltage across the replica driver stage. The gates of the first transistors are coupled to gates of second transistors that are configured to provide a scaled version of the reference current to third transistors that are included in a current mirror. The second current is received from the current comparator.

Abstract: Methods and apparatus for supplying power to a dynamic load, such as a neural network circuit. One example power supply circuit generally includes a voltage regulator circuit and a distribution circuit coupled to one or more outputs of the voltage regulator circuit. The distribution circuit is configured to output different amounts of current based on changes in the dynamic load. For certain aspects, the dynamic load includes a neural network circuit having a plurality of segments. In this case, the distribution circuit may be configured to output the different amounts of current based on which segment in the plurality of segments of the neural network circuit is active.

Abstract: A method for operating a voltage regulator is disclosed. The voltage regulator includes a first transistor and a second transistor, wherein a source of the first transistor is coupled to a supply rail, a drain of the first transistor is coupled to an output of the voltage regulator, a source of the second transistor is coupled to the output of the voltage regulator, and a drain of the second transistor is coupled to a gate of the first transistor via a feedback path. The method includes generating a current, passing the current through a resistor and a third transistor to generate a reference voltage, adjusting a resistance of the third transistor based on an output voltage at the output of the voltage regulator, and inputting the reference voltage to a gate of the second transistor.

Abstract: A continuous time linear equalizer (CTLE), comprising: a first transconductance gain circuit configured to amplify an input voltage signal with a first transconductance gain to generate a first current signal; a second transconductance gain circuit configured to amplify the input voltage signal with a second transconductance gain to generate a second current signal, wherein the second transconductance gain circuit is configured to reuse the first current signal to generate the second current signal; and at least one resistor through which the first current signal and the second current signal flow to generate an output voltage signal.

Abstract: An apparatus, such as a clock signal receiver circuit, is disclosed. The apparatus includes a common mode voltage generator configured to generate a common mode voltage at an output; an input circuit comprising: a first field effect transistor (FET); a second FET; a first capacitor coupled between a first differential clock input and a first gate of the first FET; a second capacitor coupled between a second differential clock input and a second gate of the second FET; a first resistive device coupled between the output of the common mode voltage generator and the first gate of the first FET; and a second resistive device coupled between the output of the common mode voltage generator and the second gate of the second FET; and an active inductance circuit coupled in series with the first and second FETs between an upper voltage rail and a lower voltage rail, respectively.

Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.

Abstract: A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

Abstract: A first inverter in a clock generation circuit is coupled to an input clock signal and has multiple driver slices. Each driver slice includes first transistors that have gates coupled to the input clock signal, second transistors that have sources coupled to rails of a power supply. Each of the second transistors has a drain coupled to a source of one of the first transistors. The second transistors are turned on or turned off based on signaling state of a differential enable signal. A tuning resistor is coupled to the drains of the first transistors and further coupled to an output of the first inverter. A second inverter outputs a quadrature version of the input clock signal and has an input coupled to the output of the first inverter. A first tunable capacitor is coupled to the output of the first inverter.

Abstract: A clock conditioning circuit includes a duty cycle correction circuit. The duty cycle correction circuit has a first input capacitor, a first self-biasing inverter and a variable capacitor. The first self-biasing inverter has an input coupled to the first input capacitor. The variable capacitor may be coupled to the first input capacitor. The variable capacitor may be configured to receive a first clock signal. A capacitance of the variable capacitor may be programmable by a capacitance control signal.

Abstract: A method for operating a voltage regulator is disclosed. The voltage regulator includes a first transistor and a second transistor, wherein a source of the first transistor is coupled to a supply rail, a drain of the first transistor is coupled to an output of the voltage regulator, a source of the second transistor is coupled to the output of the voltage regulator, and a drain of the second transistor is coupled to a gate of the first transistor via a feedback path. The method includes generating a current, passing the current through a resistor and a third transistor to generate a reference voltage, adjusting a resistance of the third transistor based on an output voltage at the output of the voltage regulator, and inputting the reference voltage to a gate of the second transistor.

Abstract: Methods and apparatus for supplying power to a dynamic load, such as a neural network circuit. One example power supply circuit generally includes a voltage regulator circuit and a distribution circuit coupled to one or more outputs of the voltage regulator circuit. The distribution circuit is configured to output different amounts of current based on changes in the dynamic load. For certain aspects, the dynamic load includes a neural network circuit having a plurality of segments. In this case, the distribution circuit may be configured to output the different amounts of current based on which segment in the plurality of segments of the neural network circuit is active.

Abstract: A clock conditioning circuit includes a duty cycle correction circuit. The duty cycle correction circuit has a first input capacitor, a first self-biasing inverter and a variable capacitor. The first self-biasing inverter has an input coupled to the first input capacitor. The variable capacitor may be coupled to the first input capacitor. The variable capacitor may be configured to receive a first clock signal. A capacitance of the variable capacitor may be programmable by a capacitance control signal.

Abstract: In one implementation, an apparatus, such as a clock signal receiver circuit, is disclosed. The apparatus includes a common mode voltage generator configured to generate a common mode voltage at an output; an input circuit comprising: a first field effect transistor (FET); a second FET; a first capacitor coupled between a first differential clock input and a first gate of the first FET; a second capacitor coupled between a second differential clock input and a second gate of the second FET; a first resistive device coupled between the output of the common mode voltage generator and the first gate of the first FET; and a second resistive device coupled between the output of the common mode voltage generator and the second gate of the second FET; and an active inductance circuit coupled in series with the first and second FETs between an upper voltage rail and a lower voltage rail, respectively.

Abstract: A first inverter in a clock generation circuit is coupled to an input clock signal and has multiple driver slices. Each driver slice includes first transistors that have gates coupled to the input clock signal, second transistors that have sources coupled to rails of a power supply. Each of the second transistors has a drain coupled to a source of one of the first transistors. The second transistors are turned on or turned off based on signaling state of a differential enable signal. A tuning resistor is coupled to the drains of the first transistors and further coupled to an output of the first inverter. A second inverter outputs a quadrature version of the input clock signal and has an input coupled to the output of the first inverter. A first tunable capacitor is coupled to the output of the first inverter.

Abstract: Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

Abstract: A transmitter includes driver slices coupled to its output. Each driver slice includes a first differential predriver that is selectively enabled and disabled by a first switch based on a control code configuration. A second differential predriver provides a first differential buffered data signal to a first group of driver slices when the second differential predriver is enabled. A second switch enables the second differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the first group of driver slices. A third differential predriver provides a second differential buffered data signal to a second group of driver slices when the third differential predriver is enabled. A third switch enables the third differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the second group of driver slices.

Abstract: Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

Abstract: A transmitter includes driver slices coupled to its output. Each driver slice includes a first differential predriver that is selectively enabled and disabled by a first switch based on a control code configuration. A second differential predriver provides a first differential buffered data signal to a first group of driver slices when the second differential predriver is enabled. A second switch enables the second differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the first group of driver slices. A third differential predriver provides a second differential buffered data signal to a second group of driver slices when the third differential predriver is enabled. A third switch enables the third differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the second group of driver slices.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: A duty cycle correction circuit includes four pairs of serially coupled transistors. A first two of the serial pairs of transistors couple between an internal node for complement output clock signal and ground. A second two of the serial pairs of transistors couple between the internal node and a power supply node for a power supply voltage. Each serial pair is controlled by a corresponding pair of quadrature clock signals in which one of the quadrature clock signal is delayed with respect to the other quadrature clock signal be one quarter of a clock period. The first two serial pairs of transistors thus combine to discharge the internal node for one-half clock period whereas the second two serial pairs of transistors combine to charge the internal node for one-half clock period so that the complement output clock signal has a 50% duty cycle.