Patents by Inventor Sameh Asaad

Sameh Asaad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DYNAMIC ASSIGNMENT OF DEVICE QUEUES TO VIRTUAL FUNCTIONS TO PROVIDE TO VIRTUAL MACHINES
    Publication number: 20240403134
    Abstract: Provided are a computer product, system, and method for dynamic assignment of device queues to virtual functions to provide to virtual machines. Queues are assigned to a virtual function to access the physical functions of the device. The virtual function is provided to a virtual machine to use to access the physical functions of the device. A determination is made of a utilization of the queues assigned to the virtual function accessed by the virtual machine. A number of the queues assigned to the virtual functions for requests submitted by the virtual machine is changed in response to the determined utilization.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Bharat Sukhwani, Martin Ohmacht, Hubertus Franke, Sameh Asaad, Scott Smith, Deming Chen
  • MINIMIZING HASH COLLISIONS OF COMPOSITE KEYS
    Publication number: 20240289383
    Abstract: A computer-implemented method, system and computer program product for minimizing hash collisions of composite keys. Each component (“key component”) of the composite key is converted into a linear index that uniquely represents that key component. Such a one-to-one mapping reduces the length (i.e., range of values the key component represents) of each component without introducing any collisions thereby effectively resulting in the lossless compression of the individual key components. Such a linear index for each converted key component is stored in a separate lookup memory. A reduced composite key is then created by joining together the linear indices that represent the components of the composite key thereby reducing the total length or domain (i.e., range of values the composite key represents) of the original composite key in a lossless manner. In this manner, by reducing the total length of the composite key, hash collisions of composite keys are minimized.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 29, 2024
    Inventors: Bharat Sukhwani, Sameh Asaad, Mohit Kapur
  • Non-blocking hardware function request retries to address response latency variabilities
    Patent number: 12061521
    Abstract: Managing hardware function requests incurring variable response latencies is provided. A request for a hardware function is received from a requesting program. The requested hardware function is expected to incur a variable response latency and is implemented as a main hardware function and a retry hardware function. The main hardware function is executed. It is determined whether a fixed response latency of the main hardware function has been exceeded. A response is returned with a retry flag to the requesting program. The retry flag directs the requesting program to issue a request for the retry hardware function after an interval of time. A unique identifier corresponding to the main hardware function is provided to the requesting program.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: August 13, 2024
    Assignee: International Business Machines Corporation
    Inventors: Bharat Sukhwani, Sameh Asaad, Mohit Kapur
  • On-chip logic accelerator
    Patent number: 10884949
    Abstract: Embodiments of the invention are directed to a computer-implemented method of memory acceleration. The computer-implemented method includes mapping, by a processor, an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function. The processor determines that a number of instances of request for the output function value from a logic block is less than a first threshold. The processor evicts the function row to a higher level memory.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Sameh Asaad
  • ON-CHIP LOGIC ACCELERATOR
    Publication number: 20200320018
    Abstract: Embodiments of the invention are directed to a computer-implemented method of memory acceleration. The computer-implemented method includes mapping, by a processor, an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function. The processor determines that a number of instances of request for the output function value from a logic block is less than a first threshold. The processor evicts the function row to a higher level memory.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 8, 2020
    Inventors: Bulent Abali, Sameh Asaad
  • DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS
    Publication number: 20190266149
    Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Inventors: Sameh Asaad, Robert J. Halstead, Bharat Sukhwani
  • Mapping query operations in database systems to hardware based query accelerators
    Patent number: 10127275
    Abstract: Methods and arrangements for mapping a query operation to an accelerator are provided. The method includes receiving, by a processor, a query operation and determining the design logic of the query operation, receiving a configuration of one or more available accelerators and a design logic of each of the one or more available accelerators, and determining if the query operation can be offloaded to one or more of the one or more available accelerators. Based on a determination that the query operation can be offloaded to one or more of the one or more available accelerators, the method also includes creating software structures to interface with a selected accelerator and executing the query operation on the selected accelerator. Based on a determination that the query operation cannot be offloaded to one or more of the one or more available accelerators, the method further includes executing the query operation in software.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Parijat Dube, Balakrishna R. Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Dynamically reconfigurable logic circuits using native field-programmable gate array primitives
    Patent number: 9449134
    Abstract: A method for dynamically reconfiguring logic circuits on an FPGA includes the steps of: classifying a general function into sets of static functions and modal functions to be implemented on the FPGA; for each of the modal functions, generating a list of one-active actions; devising a circuit topology including at least a subset of look-up tables (LUTs) such that any one of the modal functions can be implemented at a time on the devised circuit topology; for each modal function, associating the devised circuit topology with a controller adapted to load a LUT configuration corresponding to a prescribed one of the one-active actions; implementing a single fixed circuit on the FPGA including devised circuit topologies for each of the modal functions; and updating contents of LUTs corresponding to the LUT configuration in the devised circuit topology when a change in modal function to be implemented on the FPGA is required.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Roger Moussalli, Sameh Asaad
  • MAPPING QUERY OPERATIONS IN DATABASE SYSTEMS TO HARDWARE BASED QUERY ACCELERATORS
    Publication number: 20160012107
    Abstract: Methods and arrangements for mapping a query operation to an accelerator are provided. The method includes receiving, by a processor, a query operation and determining the design logic of the query operation, receiving a configuration of one or more available accelerators and a design logic of each of the one or more available accelerators, and determining if the query operation can be offloaded to one or more of the one or more available accelerators. Based on a determination that the query operation can be offloaded to one or more of the one or more available accelerators, the method also includes creating software structures to interface with a selected accelerator and executing the query operation on the selected accelerator. Based on a determination that the query operation cannot be offloaded to one or more of the one or more available accelerators, the method further includes executing the query operation in software.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Parijat Dube, Balakrishna R. Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Wire like link for cycle reproducible and cycle accurate hardware accelerator
    Patent number: 9002693
    Abstract: First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
    Type: Grant
    Filed: January 2, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Mohit Kapur, Benjamin D. Parker
  • Facilitating field programmable gate array accelerations of database functions
    Patent number: 8983992
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Facilitating field programmable gate array accelerations of database functions
    Patent number: 8977637
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Accelerated row decompression
    Patent number: 8838577
    Abstract: An apparatus comprises a hardware accelerator coupled to a memory. The hardware accelerator comprises one or more decompression units. The one or more decompression units are reconfigurable. The hardware accelerator may be a field-programmable gate array. The hardware accelerator may also comprise one or more reconfigurable scanner units. The one or more decompression units, in the aggregate, are operative to decompress one or more rows of a database at a bus speed of the coupling between the hardware accelerator and the memory. Two or more decompression units are operative to decompress two or more rows of a database in parallel. The apparatus allows for hardware accelerated row decompression.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bharat Sukhwani, Sameh Asaad, Balakrishna Raghavendra Iyer, Hong Min, Mathew S. Thoennes
  • Increasing throughput of multiplexed electrical bus in pipe-lined architecture
    Patent number: 8737233
    Abstract: Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sameh Asaad, Bernard V. Brezzo, Mohit Kapur
  • FACILITATING FIELD PROGRAMMABLE GATE ARRAY ACCELERATIONS OF DATABASE FUNCTIONS
    Publication number: 20140067845
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N. Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • FACILITATING FIELD PROGRAMMABLE GATE ARRAY ACCELERATIONS OF DATABASE FUNCTIONS
    Publication number: 20140067851
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N. Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • ACCELERATED ROW DECOMPRESSION
    Publication number: 20140032516
    Abstract: An apparatus comprises a hardware accelerator coupled to a memory. The hardware accelerator comprises one or more decompression units. The one or more decompression units are reconfigurable. The hardware accelerator may be a field-programmable gate array. The hardware accelerator may also comprise one or more reconfigurable scanner units. The one or more decompression units, in the aggregate, are operative to decompress one or more rows of a database at a bus speed of the coupling between the hardware accelerator and the memory. Two or more decompression units are operative to decompress two or more rows of a database in parallel. The apparatus allows for hardware accelerated row decompression.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bharat Sukhwani, Sameh Asaad, Balakrishna R. Iyer, Hong Min, Mathew S. Thoennes