Patents by Inventor Sami Rosenblatt

Sami Rosenblatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200052182
    Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Markus Brink, Jared B. Hertzberg, Sami Rosenblatt
  • Publication number: 20200052181
    Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 13, 2020
    Applicant: International Business Machines Corporation
    Inventors: Jared Barney Hertzberg, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10559564
    Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10552758
    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10551254
    Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chandrasekara Kothandaraman, Sami Rosenblatt, Akil K. Sutton
  • Publication number: 20200019068
    Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first and second films have an overlap.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Markus Brink, Sami Rosenblatt, Bryan D. Trimm
  • Patent number: 10529908
    Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10529907
    Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Jared B. Hertzberg, Sami Rosenblatt
  • Patent number: 10510943
    Abstract: Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rasit Onur Topaloglu, Sami Rosenblatt
  • Publication number: 20190378874
    Abstract: Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Inventors: Sami Rosenblatt, Jared Barney Hertzberg, Rasit Onur Topaloglu, Markus Brink
  • Patent number: 10505096
    Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu, Markus Brink
  • Patent number: 10503077
    Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first film and the second film have an overlap.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt, Bryan D. Trimm
  • Patent number: 10497746
    Abstract: Techniques related to a three-dimensional integration for qubits on crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first wafer comprising a first crystalline silicon layer attached to a first patterned superconducting layer, and a second wafer comprising a second crystalline silicon layer attached to a second patterned superconducting layer. The second patterned superconducting layer of the second wafer can be attached to the first patterned superconducting layer of the first wafer. A buried layer can comprise the first patterned superconducting layer and the second patterned superconducting layer. The buried layer can comprise one or more circuits. The superconductor structure can also comprise a transmon qubit that can comprise a Josephson junction and one or more capacitor pads comprising superconducting material. The Josephson junction can comprise a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu, Markus Brink
  • Publication number: 20190363238
    Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu, Markus Brink
  • Publication number: 20190363128
    Abstract: Techniques related to a three-dimensional integration for qubits on crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first wafer comprising a first crystalline silicon layer attached to a first patterned superconducting layer, and a second wafer comprising a second crystalline silicon layer attached to a second patterned superconducting layer. The second patterned superconducting layer of the second wafer can be attached to the first patterned superconducting layer of the first wafer. A buried layer can comprise the first patterned superconducting layer and the second patterned superconducting layer. The buried layer can comprise one or more circuits. The superconductor structure can also comprise a transmon qubit that can comprise a Josephson junction and one or more capacitor pads comprising superconducting material. The Josephson junction can comprise a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu, Markus Brink
  • Publication number: 20190348595
    Abstract: An embodiment includes a method and device for forming a multi-qubit chip. The method includes forming a plurality of qubits on a chip, where each qubit comprises a Josephson junction. The method includes annealing one or more Josephson junctions. Annealing is performed by one or more of a plurality of laser emission sources on a planar lightwave circuit. Each of the laser emission sources is located above each qubit.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Jason S. Orcutt, Sami Rosenblatt
  • Patent number: 10475983
    Abstract: Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu
  • Patent number: 10446736
    Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10445651
    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10446484
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John M. Safran, Jochonia N. Nxumalo, Joyce C. Liu, Sami Rosenblatt, Chandrasekharan Kothandaraman