Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded using solder bumps. The optically transmissive path may provide optical access to the qubit on the first chip.

Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be an aluminum/aluminum-oxide/aluminum trilayer Josephson junction on a substrate. The Josephson junction may be annealed with a thermal source. Annealing the Josephson junction may alter the frequency of the qubit.

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded. The optically transmissive path may provide optical access to the qubit on the first chip.

Abstract: An embodiment includes a method and device for forming a multi-qubit chip. The method includes forming a plurality of qubits on a chip, where each qubit comprises a Josephson junction. The method includes annealing one or more Josephson junctions. Annealing is performed by one or more of a plurality of laser emission sources on a planar lightwave circuit. Each of the laser emission sources is located above each qubit.

Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded using solder bumps. The optically transmissive path may provide optical access to the qubit on the first chip.

Abstract: A technique relates a structure. An inductive element is on a first surface. A capacitive element is on the first surface and a second surface. An interconnect structure is between the first surface and the second surface.

Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be annealed with a laser that generates a Gaussian beam. An axicon lens may be exposed to the Gaussian beam.

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

Abstract: The invention includes methods, and the structures formed, for multi-qubit chips. The methods may include annealing a Josephson junction of a qubit to either increase or decrease the frequency of the qubit. The conditions of the anneal may be based on historical conditions, and may be chosen to tune each qubit to a desired frequency.

Abstract: A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.

Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be an aluminum/aluminum-oxide/aluminum trilayer Josephson junction on a substrate. The Josephson junction may be annealed with a thermal source. Annealing the Josephson junction may alter the frequency of the qubit.

Abstract: A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.

Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.