Patents by Inventor Samir Mittal

Samir Mittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210089476
    Abstract: A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Inventors: Wei Wang, Jiangli Zhu, Ying Yu Tai, Samir Mittal
  • Publication number: 20210049101
    Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: Anirban Ray, Paul Stonelake, Samir Mittal, Gurpreet Anand
  • Publication number: 20210034241
    Abstract: Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand
  • Publication number: 20210027812
    Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Inventors: Edward McGlaughlin, Ying Yu Tai, Samir Mittal
  • Patent number: 10877892
    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand, Parag R. Maharana
  • Patent number: 10877906
    Abstract: A data bus can be determined to be in a write mode based on a prior operation transmitted over the data bus being a write operation. In response to determining that the data bus is in the write mode, a number of partition queues of a plurality of partition queues that include at least one write operation can be identified. A determination as to whether the number of partition queues of the plurality of partition queues satisfies a threshold number can be made. In response to determining that the number of partition queues satisfies the threshold number, another write operation from the plurality of partition queues can be transmitted over the data bus.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Wang, Jiangli Zhu, Ying Yu Tai, Samir Mittal
  • Patent number: 10839862
    Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Edward McGlaughlin, Ying Yu Tai, Samir Mittal
  • Publication number: 20200319813
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Patent number: 10782908
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Publication number: 20200272530
    Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
  • Patent number: 10671460
    Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
  • Publication number: 20200089629
    Abstract: A data bus can be determined to be in a write mode based on a prior operation transmitted over the data bus being a write operation. In response to determining that the data bus is in the write mode, a number of partition queues of a plurality of partition queues that include at least one write operation can be identified. A determination as to whether the number of partition queues of the plurality of partition queues satisfies a threshold number can be made. In response to determining that the number of partition queues satisfies the threshold number, another write operation from the plurality of partition queues can be transmitted over the data bus.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Inventors: Wei WANG, Jiangli ZHU, Ying Yu TAI, Samir MITTAL
  • Publication number: 20200089610
    Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 19, 2020
    Inventors: Paul STONELAKE, Horia C. SIMIONESCU, Samir MITTAL, Robert M. WALKER, Anirban RAY, Gurpreet ANAND
  • Publication number: 20200081763
    Abstract: A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Samir Mittal, Ying Yu Tai, Cheng Yuan Wu
  • Publication number: 20200081851
    Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Samir Mittal, Ying Yu Tai, Cheng Yuan Wu
  • Publication number: 20200082901
    Abstract: A processing device of a sequencer component can receive data from a controller that is external to the sequencer component. The processing device of the sequencer component can perform an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data. The code word can be stored at a memory component coupled with the sequencer component.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Samir Mittal, Ying Yu Tai, Cheng Yuan Wu, Jiangli Zhu
  • Publication number: 20200042246
    Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.
    Type: Application
    Filed: March 15, 2019
    Publication date: February 6, 2020
    Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake, Samir Mittal
  • Publication number: 20200019506
    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand, Parag R. Maharana
  • Publication number: 20190333548
    Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.
    Type: Application
    Filed: December 19, 2018
    Publication date: October 31, 2019
    Inventors: Edward McGlaughlin, Ying Yu Tai, Samir Mittal
  • Publication number: 20190243759
    Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.
    Type: Application
    Filed: October 22, 2018
    Publication date: August 8, 2019
    Inventors: Paul Stonelake, Samir Mittal