Abstract: A graph can be generated based on an access pattern associated with blocks of a memory device that have been accessed by a host system, wherein the graph comprises nodes representing at least a subset of the blocks that have been accessed by the host system and edges that are based on the access pattern, wherein each edge is associated with a respective probability value between a respective pair of nodes. A number of edges having respective probability values that satisfy a probability value threshold criterion can be determined. It can be determined whether the number of edges satisfies a decayed edge value condition. In response to determining that the number of edges does not satisfy the decayed edge value condition, the graph can be removed.

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

Abstract: A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.

Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

Abstract: Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Abstract: A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

Abstract: A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

Abstract: An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Abstract: A processing device of a sequencer component can receive data from a controller that is external to the sequencer component. The processing device of the sequencer component can perform an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data. The code word can be stored at a memory component coupled with the sequencer component.

Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

Abstract: A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Abstract: Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.