Patents by Inventor Sampath Purushothaman

Sampath Purushothaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340182
    Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 2, 2019
    Assignee: International Business Machines corporation
    Inventors: James P. Doyle, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Willi Volksen
  • Publication number: 20180374751
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Applicant: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy Ronguing Yu
  • Publication number: 20180340100
    Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.
    Type: Application
    Filed: June 8, 2018
    Publication date: November 29, 2018
    Inventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
  • Publication number: 20180337091
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Application
    Filed: July 12, 2018
    Publication date: November 22, 2018
    Applicant: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy Ronguing Yu
  • Publication number: 20180315655
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Applicant: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy RONGUING YU
  • Patent number: 9994741
    Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.
    Type: Grant
    Filed: December 13, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
  • Publication number: 20180138084
    Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 17, 2018
    Applicant: International Business Machines Corporation
    Inventors: James P. Doyle, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Will Volksen
  • Publication number: 20170271207
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Application
    Filed: August 21, 2013
    Publication date: September 21, 2017
    Applicant: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy R. Yu
  • Publication number: 20170229392
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Application
    Filed: March 17, 2017
    Publication date: August 10, 2017
    Applicant: International Business Machines Corporation
    Inventors: Sampath PURUSHOTHAMAN, Roy Ronguing Yu
  • Publication number: 20170166784
    Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.
    Type: Application
    Filed: December 13, 2015
    Publication date: June 15, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
  • Publication number: 20170154812
    Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Applicant: International Business Machines Corporation
    Inventors: James P. DOYLE, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Willi Volksen
  • Patent number: 9412620
    Abstract: Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: August 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Douglas C. La Tulipe, Jr., Sampath Purushothaman, James Vichiconti
  • Patent number: 9218956
    Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sampath Purushothaman, Anna W. Topol
  • Patent number: 9111925
    Abstract: An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Evan George Colgan, SAmpath Purushothaman, Roy R. Yu
  • Patent number: 9089080
    Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
  • Patent number: 9064717
    Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
  • Publication number: 20150147869
    Abstract: Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: Douglas C. LA TULIPE, JR., Sampath PURUSHOTHAMAN, James VICHICONTI
  • Publication number: 20150054149
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy R. Yu
  • Patent number: 8963278
    Abstract: A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. La Tulipe, Jr., Sampath Purushothaman, James Vichiconti
  • Patent number: 8962448
    Abstract: A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu