Patents by Inventor Sampath Purushothaman
Sampath Purushothaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11168234Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: GrantFiled: January 23, 2020Date of Patent: November 9, 2021Assignee: International Business Machines CorporationInventors: James L. Hedrick, Robert D. Miller, Deborah A. Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Patent number: 10796958Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: GrantFiled: July 12, 2018Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Patent number: 10777454Abstract: An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.Type: GrantFiled: July 9, 2018Date of Patent: September 15, 2020Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Patent number: 10767084Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: GrantFiled: June 8, 2018Date of Patent: September 8, 2020Assignee: International Business Machines CorporationInventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Publication number: 20200165494Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: ApplicationFiled: January 23, 2020Publication date: May 28, 2020Inventors: James L. Hedrick, Robert D. Miller, Deborah A. Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Patent number: 10651086Abstract: A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.Type: GrantFiled: August 30, 2018Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Publication number: 20190378781Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Inventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Patent number: 10340182Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.Type: GrantFiled: November 30, 2015Date of Patent: July 2, 2019Assignee: International Business Machines corporationInventors: James P. Doyle, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Willi Volksen
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Publication number: 20180374751Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: ApplicationFiled: August 30, 2018Publication date: December 27, 2018Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Ronguing Yu
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Publication number: 20180340100Abstract: The present invention related to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: ApplicationFiled: June 8, 2018Publication date: November 29, 2018Inventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Publication number: 20180337091Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: ApplicationFiled: July 12, 2018Publication date: November 22, 2018Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Ronguing Yu
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Publication number: 20180315655Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Roy RONGUING YU
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Patent number: 9994741Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: GrantFiled: December 13, 2015Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Publication number: 20180138084Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.Type: ApplicationFiled: January 5, 2018Publication date: May 17, 2018Applicant: International Business Machines CorporationInventors: James P. Doyle, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Will Volksen
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Publication number: 20170271207Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: ApplicationFiled: August 21, 2013Publication date: September 21, 2017Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Roy R. Yu
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Publication number: 20170229392Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: ApplicationFiled: March 17, 2017Publication date: August 10, 2017Applicant: International Business Machines CorporationInventors: Sampath PURUSHOTHAMAN, Roy Ronguing Yu
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Publication number: 20170166784Abstract: The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.Type: ApplicationFiled: December 13, 2015Publication date: June 15, 2017Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James L. Hedrick, Robert Dennis Miller, Deborah Ann Neumayer, Sampath Purushothaman, Mary E. Rothwell, Willi Volksen, Roy R. Yu
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Publication number: 20170154812Abstract: A process comprises insulating a porous low k substrate with an organic polymer coating where the polymer does not penetrate or substantially penetrate the pores of the substrate, e.g., pores having a pore diameter of about one nm to about 5 nm, thereby completely or substantially mitigating the potential for capacitance increase of the substrate. The substrate comprises porous microcircuit substrate materials with surface pores optionally opening into subsurface pores. The organic polymer has a molecular weight greater than about 5,000 to greater than about 10,000 and a glass transition temperature greater than about 200° C. up to about the processing temperature required for forming the imaging layer and antireflective layer in a microcircuit, e.g., greater than about 225° C. The invention includes production of a product by this process and an article of manufacture embodying these features.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Applicant: International Business Machines CorporationInventors: James P. DOYLE, Geraud Dubois, Nicholas C. Fuller, Teddie P. Magbitang, Robert D. Miller, Sampath Purushothaman, Willi Volksen
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Patent number: 9412620Abstract: Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.Type: GrantFiled: January 15, 2015Date of Patent: August 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Douglas C. La Tulipe, Jr., Sampath Purushothaman, James Vichiconti
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Patent number: 9218956Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.Type: GrantFiled: September 24, 2014Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Sampath Purushothaman, Anna W. Topol