Abstract: A system comprises a decompressor that receives an input test vector and generates an output vector in response to the input test vector. A decoder couples to the decompressor and comprises a reset pattern detector (RPD), a lookup table, and control logic. RPD scans the output vector to identify a predetermined reset pattern. The control logic couples to the RPD and the lookup table and directs operation of the lookup table in a first or second mode based on whether the output vector comprises the predetermined reset pattern, as identified by the RPD. The lookup table receives the output vector, to operate in the first mode, storing one of a plurality of codeword sets, each codeword set comprising a plurality of pairs of codewords and associated data; and to operate in the second mode, generating test data blocks in response to identified codewords in the output vector.

Abstract: A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

Abstract: Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user.

Abstract: A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.

Abstract: A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.

Abstract: A method and computer program product for providing an email navigation tool includes receiving, on an email server, an email thread including a sequence of email messages. A sender of each email message in the sequence of email messages is identified. At least one sender file associated with at least one identified sender of the email messages in the sequence of email messages is identified. The sender file is configured to provide a visual identification of the identified sender. A sequence of sender files is generated from the at least one sender file. The sequence of sender files has an order corresponding to an order of the sequence of email messages. The sequence of sender files is displayed on a computer display.

Abstract: A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for providing data pertaining to a one or more users' visits to an establishment. A location of one or more global positioning system devices is determined. Each global positioning system device is associated with a user of the device. One or more establishments situated at each determined location are identified. One or more of a time of day and a duration of the user's visit to the establishment is determined. One or more of the location, the time of day and the duration of the user's visit are recorded in a database.

Abstract: A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature.

Abstract: A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.

Abstract: A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.

Abstract: A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.

Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector.

Abstract: A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters.

Abstract: A method for automatically generating an electronic circuit layout with placed circuit elements includes receiving a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method selects a subset of circuit elements and receives placement inputs. The method generates a first placed layout configuration comprising adjusted placement parameters, based on the received placement inputs, the first placement parameters, and the design parameters. The method assigns absolute placement coordinates for each of the plurality of circuit elements based on the first placed layout configuration.

Abstract: Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.

Abstract: A computer-implemented method for performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. A step of the coordinate rotation digital computer algorithm is performed. As a result of performing the step, a value of the coordinate rotation digital computer algorithm is reduced. The value is shifted using a physical adder. A set of bits of the physical adder is disabled, wherein the set of bits corresponds to at least one high order zero of the value.

Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns.

Abstract: A method for test data compression includes generating a plurality of test cubes, each test cube comprising test cube data. Each test cube is compared with at least one other test cube, as test cube pairs, to generate a compatibility rating for each compared test cube pair. The compared test cube pair with the highest compatibility rating is determined. The compared test cube pair with the highest compatibility rating is grouped into a test cube set. The remaining test cubes are grouped into test cube sets, as test cube pairs, based on the compatibility ratings of the compared test cube pairs. For at least one test cube set, a new codeword set is generated. Test cube data is grouped into blocks based on the new codeword set. Compression for the grouped test cube data is computed. A determination is made whether compression is improved as compared to a previous codeword set. If compression is not improved, the test cube set is encoded with the new codeword set to generate an encoded test cube set.

Abstract: A system comprises a decompressor configured to receive an input test vector and to generate an output vector in response to the input test vector. A decoder couples to the decompressor and comprises a reset pattern detector, a lookup table, and control logic. The reset pattern detector (RPD) is configured to scan the output vector to identify a predetermined reset pattern. The control logic couples to the RPD and the lookup table and is configured to direct operation of the lookup table in a first mode or a second mode based on whether the output vector comprises the predetermined reset pattern, as identified by the RPD. The lookup table is configured to receive the output vector, to operate in the first mode, comprising storing one of a plurality of codeword sets, each codeword set comprising a plurality of pairs of codewords and associated data; and to operate in the second mode, comprising generating test data blocks in response to identified codewords in the output vector.