Patents by Inventor Samuel Naffziger
Samuel Naffziger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960340Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.Type: GrantFiled: November 8, 2021Date of Patent: April 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Eric J. Chapman, Stephen Victor Kosonocky, Kaushik Mazumdar, Vydhyanathan Kalyanasundharam, Samuel Naffziger, Eric M. Scott
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Patent number: 11841803Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.Type: GrantFiled: June 28, 2019Date of Patent: December 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Skyler J. Saleh, Samuel Naffziger, Milind S. Bhagavat, Rahul Agarwal
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Publication number: 20230144770Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Eric J. Chapman, Stephen Victor Kosonocky, Kaushik Mazumdar, Vydhyanathan Kalyanasundharam, Samuel Naffziger, Eric M. Scott
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Patent number: 11462294Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.Type: GrantFiled: December 14, 2020Date of Patent: October 4, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Ashish Jain, Sriram Sundaram, Samuel Naffziger
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Publication number: 20220189576Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Ashish Jain, Sriram Sundaram, Samuel Naffziger
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Publication number: 20220130342Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.Type: ApplicationFiled: December 28, 2020Publication date: April 28, 2022Inventors: ASHISH JAIN, DHIRENDRA PARTAP SINGH RANA, SAMUEL NAFFZIGER, GIA TUNG PHAN, BENJAMIN TSIEN
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Publication number: 20220059425Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Inventors: JOHN WUU, SAMUEL NAFFZIGER, PATRICK J. SHYVERS, MILIND S. BHAGAVAT, KAUSHIK MYSORE, BRETT P. WILKERSON
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Patent number: 11189540Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: GrantFiled: September 6, 2019Date of Patent: November 30, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Patent number: 11164807Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: GrantFiled: September 6, 2019Date of Patent: November 2, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Patent number: 11054883Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.Type: GrantFiled: June 18, 2018Date of Patent: July 6, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Leonardo De Paula Rosa Piga, Samuel Naffziger, Ivan Matosevic, Indrani Paul
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Publication number: 20200409859Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Skyler J. SALEH, Samuel NAFFZIGER, Milind S. BHAGAVAT, Rahul AGARWAL
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Patent number: 10644826Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.Type: GrantFiled: February 23, 2018Date of Patent: May 5, 2020Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Samuel Naffziger, Michael K. Ciraula, Russell Schreiber
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Publication number: 20190393124Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: September 6, 2019Publication date: December 26, 2019Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Publication number: 20190393123Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: September 6, 2019Publication date: December 26, 2019Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Patent number: 10452554Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.Type: GrantFiled: April 8, 2016Date of Patent: October 22, 2019Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Ihab Amer, Khaled Mammou, Haibo Liu, Edward Harold, Fabio Gulino, Samuel Naffziger, Gabor Sines, Lawrence A. Bair, Andy Sung, Lei Zhang
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Patent number: 10431517Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: GrantFiled: August 25, 2017Date of Patent: October 1, 2019Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Publication number: 20190268086Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Applicant: Advanced Micro Devices, Inc.Inventors: John Wuu, Samuel Naffziger, Michael K. Ciraula, Russell Schreiber
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Patent number: 10303398Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.Type: GrantFiled: October 26, 2017Date of Patent: May 28, 2019Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Michael K. Ciraula, Russell Schreiber, Samuel Naffziger
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Publication number: 20190129651Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Inventors: John WUU, Michael K. CIRAULA, Russell SCHREIBER, Samuel NAFFZIGER
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Publication number: 20190067152Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson