Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

Abstract: Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F<Pmax/(CV2), where C is a switching capacitance and where Pmax is a predetermined maximum power consumption of the core chip circuitry. The integrated circuit also includes means for providing a clock signal having frequency F to the circuit.

Abstract: An integrated circuit is provided which in one embodiment includes a first sub-circuit coupled to a first power supply rail providing a first power supply voltage; a second sub-circuit coupled to a second power supply rail providing a second power supply voltage; and first power supply modulation means, coupled to the first sub-circuit, for modulating the first power supply voltage without modulating the second power supply voltage.

Abstract: A memory system includes a first plurality of memory cells, wherein each of the first plurality of memory cells includes a first node and a second node that are configured to have opposite logic values, and a second plurality of memory cells, wherein each of the second plurality of memory cells includes a first node and a second node that are configured to have opposite logic values. Providing a pre-program data value to the first nodes of the first plurality of memory cells, and to the second nodes of the second plurality of memory cells enables the memory system to be pre-programmed.

Abstract: A multiple processor integrated circuit has a first processor-first level cache combination powered by a first power terminal, and a second processor-first level cache combination powered by a second power terminal. There is common circuitry coupled to each processor-cache combination. In a particular embodiment, the processor-cache combinations are capable of receiving independently controlled power over the power terminals.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: Systems and methods are provided for generating a current. A first current source generates a first current based on a first current selection signal, and a second current source generates a second current that is a multiple of the first current in response to selection of the first current.

Abstract: In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first controller for controlling a frequency of operation of the clock generator in response to the at least one sensor, wherein the first controller further controls the frequency of operation in response to communication of frequency adjustments from first controllers in other clock zones within one cycle of latency, and a second controller that provides an overdrive signal, that is combined with adjustment signals from the first controller for the clock generator, in response to communication of frequency adjustments from other clock zones beyond one cycle of latency.

Abstract: One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones.

Abstract: A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.

Abstract: A system and method can mitigate voltage fluctuations. According to one embodiment, a delay system provides a delayed version of a first reference signal as a function of a supply voltage. A comparator provides a control signal for controlling a protection device based on the delayed version of the first reference signal and a second reference signal. The amount of delay provided by the delay system defines a threshold based on which the comparator provides the control signal.

Abstract: Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations to determine power consumption associated with non-conventional circuits in the circuit design. The power characterizations can be determined prior to circuit design timing analysis, stored and utilized during circuit design timing analysis. The power estimates associated with the non-conventional circuits can be added to power estimates associated with the conventional circuits of the circuit design to compute a power associated with the circuit design.

Abstract: Systems and methods are disclosed for controlling an associated circuit. A clock waveform that transitions between normally high and low levels over a cycle in a first operating mode is provided to the associated circuit. The clock waveform is modified to include an intermediate level between the normally high and low levels over a cycle in a second operating mode.

Abstract: A system and method for measuring integrated circuit processor power demand comprises calibrating one or more voltage controlled oscillators for use as ammeters, calibrating a calibration current source, wherein the calibration current source draws current through a inherent resistance, calibrating the inherent resistance, and interleaving said calibrations in time with calculating the processor power demand using a voltage that is measured across the inherent resistance.

Abstract: Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.

Abstract: The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

Abstract: A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.

Abstract: An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of the invention is directed to a method for monitoring and controlling an integrated circuit comprising providing an embedded micro-controller on a same VLSI die as the integrated circuit, monitoring and controlling a VLSI environment of the integrated circuit with the embedded micro-controller.