Patents by Inventor Samuele Sciarrillo
Samuele Sciarrillo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187389Abstract: To manufacture a redistribution layer for an integrated circuit, a first insulating layer is formed on a conductive interconnection layer of a wafer. A conductive body is then formed in electrical contact with the interconnection layer. The conductive body is then covered with an insulating region having an aperture that exposes a surface of the conductive body. The surface of the conductive body and the insulating region are then covered with an insulating protection layer having a thickness less than 100 nm. This insulating protection layer is configured to provide a protection against oxidation and/or corrosion of the conductive body.Type: ApplicationFiled: December 9, 2022Publication date: June 15, 2023Applicant: STMicroelectronics S.r.l.Inventors: Samuele SCIARRILLO, Paolo COLPANI
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Patent number: 11600665Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.Type: GrantFiled: October 13, 2020Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventors: Marcello Ravasio, Samuele Sciarrillo, Fabio Pellizzer, Innocenzo Tortorelli, Roberto Somaschini, Cristina Casellato, Riccardo Mottadelli
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Patent number: 11587866Abstract: A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.Type: GrantFiled: August 21, 2020Date of Patent: February 21, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Francesco Maria Pipia, Ivan Venegoni, Annamaria Votta, Francesca Milanesi, Samuele Sciarrillo, Paolo Colpani
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Publication number: 20230005848Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo COLPANI, Samuele SCIARRILLO, Ivan VENEGONI, Francesco Maria PIPIA, Simone BOSSI, Carmela CUPETA
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Publication number: 20220384371Abstract: A redistribution layer for an integrated circuit is made by forming a conductive interconnection layer; forming a conductive body in electrical contract with the interconnection layer; and covering the conductive body with a first coating layer having a thickness less than 100 nm. The first coating layer is configured to provide a protection against oxidation and/or corrosion of the conductive body. To carry out an electrical test of the integrated circuit, a testing probe locally perforates the first coating layer until the conductive body is electrically contacted by the testing probe.Type: ApplicationFiled: May 23, 2022Publication date: December 1, 2022Applicant: STMicroelectronics S.r.l.Inventors: Samuele SCIARRILLO, Paolo COLPANI
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Patent number: 11469194Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.Type: GrantFiled: August 7, 2019Date of Patent: October 11, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Paolo Colpani, Samuele Sciarrillo, Ivan Venegoni, Francesco Maria Pipia, Simone Bossi, Carmela Cupeta
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Patent number: 11011579Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.Type: GrantFiled: August 24, 2018Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventor: Samuele Sciarrillo
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Publication number: 20210091140Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.Type: ApplicationFiled: October 13, 2020Publication date: March 25, 2021Inventors: Marcello Ravasio, Samuele Sciarrillo, Fabio Pellizzer, Innocenzo Tortorelli, Roberto Somaschini, Cristina Casellato, Riccardo Mottadelli
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Patent number: 10910437Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.Type: GrantFiled: May 23, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventors: Ombretta Donghi, Marcello Ravasio, Samuele Sciarrillo, Roberto Somaschini
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Patent number: 10886332Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.Type: GrantFiled: January 7, 2020Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventors: Samuele Sciarrillo, Marcello Ravasio
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Publication number: 20200388569Abstract: An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.Type: ApplicationFiled: August 21, 2020Publication date: December 10, 2020Inventors: Francesco Maria PIPIA, Ivan VENEGONI, Annamaria VOTTA, Francesca MILANESI, Samuele SCIARRILLO, Paolo COLPANI
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Patent number: 10854675Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.Type: GrantFiled: August 15, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventor: Samuele Sciarrillo
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Patent number: 10854674Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.Type: GrantFiled: August 31, 2017Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Marcello Ravasio, Samuele Sciarrillo, Fabio Pellizzer, Innocenzo Tortorelli, Roberto Somaschini, Cristina Casellato, Riccardo Mottadelli
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Patent number: 10790226Abstract: An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.Type: GrantFiled: July 24, 2018Date of Patent: September 29, 2020Assignee: STMICROELECTRONICS S.r.l.Inventors: Francesco Maria Pipia, Ivan Venegoni, Annamaria Votta, Francesca Milanesi, Samuele Sciarrillo, Paolo Colpani
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Patent number: 10777743Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.Type: GrantFiled: October 25, 2017Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Marcello Ravasio, Samuele Sciarrillo, Andrea Gotti
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Publication number: 20200144329Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.Type: ApplicationFiled: January 7, 2020Publication date: May 7, 2020Inventors: Samuele Sciarrillo, Marcello Ravasio
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Patent number: 10593625Abstract: A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.Type: GrantFiled: July 27, 2018Date of Patent: March 17, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Samuele Sciarrillo, Ivan Venegoni, Paolo Colpani, Francesca Milanesi
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Patent number: 10573689Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.Type: GrantFiled: December 7, 2018Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Samuele Sciarrillo, Marcello Ravasio
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Patent number: 10566283Abstract: A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.Type: GrantFiled: July 27, 2018Date of Patent: February 18, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Samuele Sciarrillo, Paolo Colpani, Ivan Venegoni
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Publication number: 20200051935Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.Type: ApplicationFiled: August 7, 2019Publication date: February 13, 2020Inventors: Michele MOLGG, Cosimo CIMINELLI, Paolo COLPANI, Samuele SCIARRILLO, Ivan VENEGONI, Francesco Maria PIPIA, Simone BOSSI, Carmela CUPETA