Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

Abstract: An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.

Abstract: A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

Abstract: An integrated device includes a semiconductor body and a dielectric layer bounded by a surface. A conductive region of a first metal material forms a via region extending into a hole passing through the dielectric layer, and an overlaid redistribution region which extends over the surface. At least one barrier region of a second metal material extends into the hole and surrounds the via region, and the barrier region furthermore extending over the surface. A first coating layer of a third metal material covers the top and the sides of an upper portion of the redistribution region at a distance from the surface. A second coating layer of a fourth metal material extends at a distance from the surface and covers the first coating layer, and covers laterally a lower portion of the redistribution region which is disposed on top of portions of the barrier region extending over the surface.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material.

Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.