Patents by Inventor Samuli Laine

Samuli Laine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200051316
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Samuli LAINE, Tero KARRAS, Greg MUTHLER, William Parsons NEWHALL, JR., Ronald Charles BABICH, Ignacio LLAMAS, John BURGESS
  • Publication number: 20200051312
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Greg Muthler, Tero Karras, Samuli Laine, William Parsons Newhall, JR., Ronald Charles Babich, JR., John Burgess, Ignacio Llamas
  • Publication number: 20200051315
    Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Samuli Laine, Timo AILA, Tero KARRAS, Gregory MUTHLER, William Parsons NEWHALL, JR., Ronald Charles BABICH, JR., Craig KOLB, Ignacio LLAMAS
  • Publication number: 20200050550
    Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Greg MUTHLER, Timo AILA, Tero KARRAS, Samuli LAINE, William Parsons NEWHALL, Ronald Charles BABICH, John BURGESS, Ignacio LLAMAS
  • Publication number: 20200050451
    Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Ronald Babich, John BURGESS, Jack CHOQUETTE, Tero KARRAS, Samuli LAINE, Ignacio LLAMAS, Gregory MUTHLER, William Parsons NEWHALL, JR.
  • Publication number: 20200051314
    Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Samuli Laine, Tero Karras, Timo Aila, Robert Ohannessian, William Parsons Newhall, JR., Greg Muthler, Ian Kwong, Peter Nelson, John Burgess
  • Patent number: 9437039
    Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 6, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine, Tero Karras, David Luebke
  • Patent number: 9269183
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a bilinear approximation per primitive for a screen space region which is to be rendered, wherein the screen space region includes a plurality of sample points. The bilinear approximation is used to estimate coverage of a predefined primitive against one or more sample points within the screen space region. At least one sample point in the screen space region which is not covered by the predefined primitive is excluded from testing in the rendering of the screen space region.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: February 23, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Samuli Laine, Tero Karras
  • Patent number: 9269182
    Abstract: A method for identifying entry points of a hierarchical structure having a plurality of nodes includes the operations selecting a node of a hierarchical structure and testing it for identification as an entry point. The node is identified as an entry point, and the selection, testing, and identification operations are repeated for at least one additional node of the hierarchical structure to identify at least a second node as a respective second entry point for the hierarchical structure.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: February 23, 2016
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 9153068
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending in an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 6, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Samuli Laine, Tero Karras, Jaakko Lehtinen, Timo Aila
  • Patent number: 9147270
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive in a three dimensional coordinate system, the coordinate system including a screen space dimension, a lens dimension and a time dimension. A bounding volume is constructed for a screen space region which is to be rendered, the bounding volume overlapping a portion of the screen space region. The bounding volume is defined according to a plurality of bounding planes which extend in the three dimensional coordinate system, whereby the bounding planes are determined as a function of the trajectory of the primitive. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 29, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine
  • Patent number: 9142043
    Abstract: A method for reducing the number of samples tested for rendering a screen space region of an image includes constructing a trajectory of a primitive extending within an image which is to be rendered. A bounding volume is constructed for a screen space region of the image, the bounding volume characterized as having a bound in a non-screen space dimension which is defined as a function of the primitive's trajectory. The bounding volume is further characterized as overlapping a portion of the screen space region which is to be rendered. One or more sample points which are located within the screen space region, and which are not overlapped by the bounding volume are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 22, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Timo Aila, Samuli Laine, Tero Karras, Jaakko Lehtinen, Peter Shirley
  • Patent number: 8977049
    Abstract: A method for estimating signal-dependent noise includes defining a plurality of pixel groups from among the image pixels. The method further includes computing, for one or more signal levels of the image, a difference value between two pixel groups, whereby a respective one or more difference values are computed collectively. The method determines an estimated noise response of the image as a function of the one or more computed difference values.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: March 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 8970584
    Abstract: A bounding box-based method for reducing the number of samples tested for rendering a screen space region of an image includes determining a trajectory of a primitive in screen space for an image which is to be rendered and constructing an axis-aligned bounding box for the screen space region. The axis-aligned bounding box includes a bound in a non-screen dimension that is defined as a function of the screen space trajectory of the primitive, and overlaps a portion of the screen space region. One or more sample points which are located within the screen space region, and which are not overlapped by the axis-aligned bounding box are excluded from testing.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 3, 2015
    Assignee: Nvidia Corporation
    Inventors: Timo Aila, Jaakko Lehtinen, Peter Shirley, Samuli Laine
  • Patent number: 8842931
    Abstract: A system, method, and computer program product are provided for reducing noise in an image using depth-based on sweeping over image samples. In use, each noisy pixel of an image having noise is identified. Additionally, for each noisy pixel, at least one sample included in each of a plurality of neighboring pixels to the noisy pixel is identified. Furthermore, the samples are swept over at least partially in a depth-based order to identify a value for the noisy pixel that reduces the noise.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: September 23, 2014
    Assignee: NVIDIA Corporation
    Inventors: Peter Schuyler Shirley, Timo Aila, Jonathan Michael Cohen, Eric B. Enderton, Samuli Laine, Morgan McGuire, David Patrick Luebke
  • Patent number: 8698836
    Abstract: A system, method, and computer program product are provided for optimizing stratified sampling associated with stochastic transparency. In use, surface data associated with one or more surfaces to be rendered is received. Additionally, the one or more surfaces are rendered, utilizing stochastic transparency, where stratified sampling associated with the stochastic transparency is optimized.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: April 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: Samuli Laine, Tero Karras
  • Publication number: 20140071129
    Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.
    Type: Application
    Filed: December 28, 2012
    Publication date: March 13, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jaakko Lehtinen, Timo Aila, Samuli Laine, Tero Karras, David Luebke
  • Patent number: 8564589
    Abstract: A method for performing a ray-box intersection test includes forming a span extending between a first plane-ray intersection point and a second plane-ray intersection point, and increasing the span by relocating to a new position at least one of the first and second plane-ray intersection points. A box intersection span is constructed using the increased span, and the box intersection span, which corresponds to a node in a hierarchical acceleration structure, is tested for intersection with the ray.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 22, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine, John Erik Lindholm
  • Patent number: 8555036
    Abstract: A system includes a processor having an instruction register for storing an instruction having a predefined opcode, a predicate register for storing a predicate condition to select an output register for a result of the instruction, a first output register, and a second output register. The processor further includes processor circuitry operable to execute the instruction to produce a result, and processor circuitry operable to store the result of the instruction in the first output register if the predicate condition to select the output is true, and to store the second output register if the predicate condition to select the output is false. A single instruction is used to produce the result, and to store the result of the instruction.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 8, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine
  • Patent number: 8502819
    Abstract: A method for performing a ray tracing node traversal operation in an image rendering process includes traversing a plurality of nodes within spatial hierarchy that represents a scene which is to be rendered, the spatial hierarchy including two or more hierarchy levels, each hierarchy level including one or more nodes. A number representing the number of nodes traversed in each one of a plurality of different hierarchy levels is stored, wherein each number is represented by at least one bit in a multi-bit binary sequence.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 6, 2013
    Assignee: NVIDIA Corporation
    Inventors: Timo Aila, Samuli Laine, John Erik Lindholm