Abstract: The present invention relates to a composition for preventing, improving, or treating diseases related to advanced glycation end products, comprising an indole derivative or a pharmaceutically acceptable salt thereof. Specifically, the composition of the present invention possesses the effect of trapping methylglyoxal (MGO), which is a main precursor of advanced glycation end products, and thus can be effectively used for preventing, improving, or treating diseases related to advanced glycation end products.

Abstract: The present invention relates to a novel indole derivative and a use thereof. The novel indole derivative according to the present invention traps methylglyoxal (MGO), which is a main precursor of advanced glycation end products, and thus can be effectively used for preventing, improving, or treating diseases related to advanced glycation end products.

Abstract: A semiconductor die including a crack stop structure, at least one edge seal structure and a selector circuit is provided. The crack stop structure is located in a periphery region of the semiconductor die. The crack stop structure is biased by a first voltage. The edge seal structure is located between the crack stop structure and an integrated circuit region of the semiconductor die. The edge seal structure is biased by the first voltage in a normal mode and is biased by a second voltage different from the first voltage in a test mode. The selector circuit receives the first voltage, the second voltage and a control signal for placing the semiconductor die in the normal mode or the test mode, and selects and outputs one of the first voltage and the second voltage to the edge seal structure according to the control signal.

Abstract: A semiconductor die including a crack stop structure, at least one edge seal structure and a selector circuit is provided. The crack stop structure is located in a periphery region of the semiconductor die. The crack stop structure is biased by a first voltage. The edge seal structure is located between the crack stop structure and an integrated circuit region of the semiconductor die. The edge seal structure is biased by the first voltage in a normal mode and is biased by a second voltage different from the first voltage in a test mode. The selector circuit receives the first voltage, the second voltage and a control signal for placing the semiconductor die in the normal mode or the test mode, and selects and outputs one of the first voltage and the second voltage to the edge seal structure according to the control signal.

Abstract: A memory device is provided. The memory device includes: a plurality of subarrays, a row control, a column control, a plurality of sense amplifiers, a plurality of sub word drivers, and a repeater. Each of the subarrays are electrically coupled to each other. The row control is configured to control at least a row of the subarrays. The column control is configured to control at least one column of the subarrays. The sense amplifiers are adapted to each of the subarrays are periodically enabled during a data access operation. The sub word drivers are disposed adjacent to each of the subarrays and provides a driving signal corresponds to the subarrays. The repeater is configured to disposed on the edge of the subarrays.

Abstract: A memory device is provided. The memory device includes: a plurality of subarrays, a row controller, a column controller, a plurality of sense amplifiers, a plurality of sub word line drivers, and a plurality of logic circuits. Each of the subarrays are electrically coupled to each other. The row controller is configured to control at least a row of the subarrays. The column controller is configured to control at least one column of the subarrays. The sense amplifiers are adapted to each of the subarrays are enabled during a data access operation. The sub word line drivers are disposed adjacent to each of the subarrays and provides a driving signal corresponds to the subarrays. The plurality of logic circuits is disposed in the subarrays and configured to perform the data access operation.

Abstract: A memory device is provided. The memory device includes: a plurality of subarrays, a row control, a column control, a plurality of sense amplifiers, a plurality of sub word drivers, and a repeater. Each of the subarrays are electrically coupled to each other. The row control is configured to control at least a row of the subarrays. The column control is configured to control at least one column of the subarrays. The sense amplifiers are adapted to each of the subarrays are periodically enabled during a data access operation. The sub word drivers are disposed adjacent to each of the subarrays and provides a driving signal corresponds to the subarrays. The repeater is configured to disposed on the edge of the subarrays.

Abstract: A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.

Abstract: The disclosure is directed to a memory storage device and an automatic error repair method thereof. In an aspect, the memory storage device includes a connection interface configured to receive a write command and a word line address associated with the write command, a memory array including a memory bank which contains an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address, a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells, and a memory control circuit configured to transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

Abstract: A volatile memory and a method for efficient bulk data movement, backup operation in the volatile memory device are provided. The volatile memory device includes: a plurality of subarray, configured to access data, wherein each of the subarray is electrically coupled to each other. The row address control, configured to control the row of each of the plurality of subarray. The column control, configured to control the column of each of the plurality of subarray. The plurality of sense amplifier, adapted to each of the plurality of sub array is periodically enabled during the data access operation. The plurality of sub word driver, adapted on the adjacent to the plurality of sub array provides a driving signal to the corresponding word line in the plurality of subarray. The volatile memory device performs a data movement operation in a predetermined block and determine an odd data and an even data in the predetermined block.

Abstract: A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.

Abstract: A volatile memory and a method for efficient bulk data movement, backup operation in the volatile memory device are provided. The volatile memory device includes: a plurality of subarray, configured to access data, wherein each of the subarray is electrically coupled to each other. The row address control, configured to control the row of each of the plurality of subarray. The column control, configured to control the column of each of the plurality of subarray. The plurality of sense amplifier, adapted to each of the plurality of sub array is periodically enabled during the data access operation. The plurality of sub word driver, adapted on the adjacent to the plurality of sub array provides a driving signal to the corresponding word line in the plurality of subarray. The volatile memory device performs a data movement operation in a predetermined block and determine an odd data and an even data in the predetermined block.

Abstract: A memory device includes a memory array including a plurality of memory cells coupled to a plurality of bitlines and a plurality of wordlines and a plurality of sense amplifier circuits coupled to the plurality of bitlines. Each sense amplifier circuit includes a sense amplifier configured to sense and amplify a voltage difference between two of the bitlines coupled thereto. The memory device further includes an address decoder to receive and decode addresses of memory cells to enable corresponding bitlines and wordlines, a refresh controller to control data refreshing of the memory cells, and a mode controller to control the memory device to operate in different operating modes including a deep power down (DPD) mode. The mode controller controls data of a group of the memory cells, sensed by corresponding ones of the sense amplifier circuits, to be latched in the corresponding sense amplifier circuits when entering the DPD mode.

Abstract: A delaying circuit is capable of constantly maintaining its delay regardless of process condition or voltage variation and a pulse generating circuit uses the delaying circuit. The delay circuit for delaying a signal that is inputted to an input stage by a predetermined time to output to an output stage, comprises a pull-up unit for pulling up the output stage in response to the signal that is inputted to the input stage, the pull-up unit including a first resistor device and a first MOS transistor that is maintained in turn-on state and is coupled to the first resistor device in parallel to delay the signal that is inputted to the input stage by the predetermined time; and a pull-down unit for pulling down the output stage in response to the signal that is inputted to the input stage.

Abstract: A semiconductor memory device operates at a high speed regardless of variance of power voltage or process change, by consistently keeping variance of the skew between the transfer path of the address and the transfer path of internal operation of the memory device. The semiconductor memory device comprises a memory core for outputting data corresponding an inputted address, a data output buffer for outputting the data that is outputted from the memory core to external, a data transferring unit for transferring the data that is outputted from the memory core to the data output buffer in response to an internal address, and an address transferring unit for receiving the address and passing the received address through an address transfer path that copies a data transfer path through which the data is transferred by the data transferring unit to output the address as the internal address.

Abstract: A delaying circuit is capable of constantly maintaining its delay regardless of process condition or voltage variation and a pulse generating circuit uses the delaying circuit. The delay circuit for delaying a signal that is inputted to an input stage by a predetermined time to output to an output stage, comprises a pull-up unit for pulling up the output stage in response to the signal that is inputted to the input stage, the pull-up unit including a first resistor device and a first MOS transistor that is maintained in turn-on state and is coupled to the first resistor device in parallel to delay the signal that is inputted to the input stage by the predetermined time; and a pull-down unit for pulling down the output stage in response to the signal that is inputted to the input stage.

Abstract: A semiconductor memory device operates at a high speed regardless of variance of power voltage or process change, by consistently keeping variance of the skew between the transfer path of the address and the transfer path of internal operation of the memory device. The semiconductor memory device comprises a memory core for outputting data corresponding an inputted address, a data output buffer for outputting the data that is outputted from the memory core to external, a data transferring unit for transferring the data that is outputted from the memory core to the data output buffer in response to an internal address, and an address transferring unit for receiving the address and passing the received address through an address transfer path that copies a data transfer path through which the data is transferred by the data transferring unit to output the address as the internal address.

Abstract: An equalizing and precharging circuit in a semiconductor memory device includes a pull down equalizing and precharging unit for equalizing and precharging data lines in response to an input/output equalizing signal and a pull up equalizing and precharging unit for equalizing and precharging data lines in response to an input/output equalizing bar signal.

Abstract: A semiconductor memory device employing a BSG circuit to thereby improve a sensing speed by additionally securing an operational voltage of a sense amplifier in a low voltage operation. The semiconductor memory device includes a sense amplifier for amplifying memory cell data, a sense amplifier driving unit for driving a pull-up source line and a pull-down source line of the sense amplifier and sequentially driving the pull-down source line into a ground voltage and a boosted ground voltage in response to a first control signal and a second control signal, a sense amplifier driving control unit for generating the first and the second control signals and setting a ground voltage driving time of the pull-down source line by adjusting timing of the first control signal, and a boosted ground voltage generating unit for producing the boosted ground voltage.

Abstract: A bitline precharge circuit and a method for precharging bitlines in a semiconductor memory device are described herein. The bitline precharge circuit includes a driving control unit configured to output a VDD driving signal and a VPP driving signal in response to a bitline precharge enable signal, a precharge circuit driving unit configured to output bitline precharge signal of a power supply voltage VDD level or a boosted voltage VPP level in response to the VDD driving signal or the VPP driving signal, and a bitline precharge unit configured to precharge bitlines in response to the bitline precharge signal. A voltage level of the bitline precharge signal reaches the VDD level for a predetermined time from an enabled starting point of the bitline precharge enable signal, and then the voltage level of the bitline precharge signal reaches the VPP level after the predetermined time.