Abstract: A bitline precharge circuit and a method for precharging bitlines in a semiconductor memory device are described herein. The bitline precharge circuit includes a driving control unit configured to output a VDD driving signal and a VPP driving signal in response to a bitline precharge enable signal, a precharge circuit driving unit configured to output bitline precharge signal of a power supply voltage VDD level or a boosted voltage VPP level in response to the VDD driving signal or the VPP driving signal, and a bitline precharge unit configured to precharge bitlines in response to the bitline precharge signal. A voltage level of the bitline precharge signal reaches the VDD level for a predetermined time from an enabled starting point of the bitline precharge enable signal, and then the voltage level of the bitline precharge signal reaches the VPP level after the predetermined time.

Abstract: A semiconductor memory device includes a memory cell, a sense amplifying means for driving a bit line during a writing operation in the memory cell and a write driving means for providing data in response to a write command signal. The memory device also includes a power driving means for providing a pull-down voltage and a pull-up voltage to the sense amplifying means in response to a bit line activation signal and a write command signal. The power driving means provides a ground voltage as the pull-down voltage and selectively provides one of a cell power supply voltage and a high voltage as the pull-up voltage.

Abstract: A semiconductor memory device employing a BSG circuit to thereby improve a sensing speed by additionally securing an operational voltage of a sense amplifier in a low voltage operation. The semiconductor memory device includes a sense amplifier for amplifying memory cell data, a sense amplifier driving unit for driving a pull-up source line and a pull-down source line of the sense amplifier and sequentially driving the pull-down source line into a ground voltage and a boosted ground voltage in response to a first control signal and a second control signal, a sense amplifier driving control unit for generating the first and the second control signals and setting a ground voltage driving time of the pull-down source line by adjusting timing of the first control signal, and a boosted ground voltage generating unit for producing the boosted ground voltage.

Abstract: An equalizing and precharging circuit in a semiconductor memory device includes a pull down equalizing and precharging unit for equalizing and precharging data lines in response to an input/output equalizing signal and a pull up equalizing and precharging unit for equalizing and precharging data lines in response to an input/output equalizing bar signal.

Abstract: A semiconductor memory device includes a memory cell, a sense amplifying means for driving a bit line during a writing operation in the memory cell and a write driving means for providing data in response to a write command signal. The memory device also includes a power driving means for providing a pull-down voltage and a pull-up voltage to the sense amplifying means in response to a bit line activation signal and a write command signal. The power driving means provides a ground voltage as the pull-down voltage and selectively provides one of a cell power supply voltage and a high voltage as the pull-up voltage.

Abstract: A circuit for controlling an equalization pulse width is disclosed that enables a stable data and minimizes or reduces a speed delay. The control circuit for the equalization pulse width includes a pulse generator for forming a predetermined pulse width in accordance with a set option when address signals are transited, and an addition unit for combining pulses formed by each of the address signals. A pulse latch unit continuously latches an equalization signal in an enabled state when signals are all enabled using a signal by which a redundancy Y-selection signal is enabled when a redundancy occurs in a coding signal from a Y-predecoder.

Abstract: The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the plurality of normal memory cells and the redundancy data stored in the plurality of redundancy memory cells are outputted through a local normal input/output line and a local redundancy input/output line, respectively. The column redundancy unit outputs a redundancy enable signal according to a column address, a row address, and a state of a fuse.

Abstract: A circuit controls data input/output buffers, where an input buffer is disabled during a read mode for reducing power consumption. In a preferred embodiment, a data input buffer is enabled in response to a control signal to receive data from an input/output pad. A data output buffer provides data to the input/output pad in response to the control signal. A data input/output buffer control unit generates the control signal to disable the data input buffer and enable the data output buffer in read mode. Preferably, the circuit is readily applicable to a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM).

Abstract: The present invention relates to a column redundancy circuit for a semiconductor memory whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the normal memory cells and the redundancy data stored in the redundancy memory cells are outputted to a switch unit. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the normal data or redundancy data from the memory array, and outputs it to a main amplifier.

Abstract: An amplifier is provided that includes a current amplifying and current/voltage converting part that performs current amplification with respect to signals received from a first data bus and a second data bus. The current amplifying and current/voltage converting part further converts the amplified signal currents into a voltage. The amplifier further includes a voltage amplifying part that amplifies the voltage from the current amplifying part and current/voltage converting part to produce an amplified output.

Abstract: The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The redundancy data stored in the redundancy memory cells are outputted to a first main amplifier, and the normal data stored in the normal memory cells are outputted to a second main amplifier. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the redundancy data from the first main amplifier or the normal data from the second amplifier, and outputs it to a data output buffer.

Abstract: An overdriving control circuit includes a comparator for receiving a sense amplifier enable signal and comparing a voltage of bit line or bit bar line with a reference voltage, and a sense amplifier driving unit for logically combining the sense amplifier enable signal and an output signal of the comparator and outputting a control signal of a switch which selectively supplies an internal voltage and an external voltage. The circuit senses a variation of the external voltage or a bouncing of source voltage and controls the overdriving region, thereby obtaining a sufficient overdriving region and accelerating the operation of a sense amplifier.