Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A semiconductor storage device comprises a memory block including first and second memory cells, first and second word lines electrically connected to the first and second memory cells, respectively, first and second booster circuits, and a control circuit. During a read operation in which the first word line is a selected word line, the control circuit controls the first booster circuit to start boosting the output voltage thereof before a target block address associated with the read command is determined, causes the output voltage of the first booster circuit to be supplied to the first and second word lines, controls the second booster circuit to start boosting the output voltage thereof, and causes the output voltage of the second booster circuit, instead of the output voltage of the first booster circuit, to be supplied to the first word line.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor storage device comprises a memory block including first and second memory cells, first and second word lines electrically connected to the first and second memory cells, respectively, first and second booster circuits, and a control circuit. During a read operation in which the first word line is a selected word line, the control circuit controls the first booster circuit to start boosting the output voltage thereof before a target block address associated with the read command is determined, causes the output voltage of the first booster circuit to be supplied to the first and second word lines, controls the second booster circuit to start boosting the output voltage thereof, and causes the output voltage of the second booster circuit, instead of the output voltage of the first booster circuit, to be supplied to the first word line.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor storage device includes a word line and a wiring, a first transistor controlled to connect the word line to the wiring, a first booster circuit configured to boost an output voltage thereof to a first voltage, a second transistor controlled to connect the first booster circuit to the wiring, and a control circuit configured to control the first booster circuit, and the first and second transistors during a read operation. During the read operation, the control circuit controls the first booster circuit to start boosting its output voltage to the first voltage while controlling the second transistor to connect the output of the first booster circuit to the wiring so that a voltage of the wiring rises together with the output voltage. After the output voltage has reached the first voltage, the control circuit controls the first transistor to connect the word line to the wiring.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: A semiconductor storage device includes a word line and a wiring, a first transistor controlled to connect the word line to the wiring, a first booster circuit configured to boost an output voltage thereof to a first voltage, a second transistor controlled to connect the first booster circuit to the wiring, and a control circuit configured to control the first booster circuit, and the first and second transistors during a read operation. During the read operation, the control circuit controls the first booster circuit to start boosting its output voltage to the first voltage while controlling the second transistor to connect the output of the first booster circuit to the wiring so that a voltage of the wiring rises together with the output voltage. After the output voltage has reached the first voltage, the control circuit controls the first transistor to connect the word line to the wiring.

Abstract: According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal, a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal, a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor, a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to an output terminal, a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor b